Public Version
McSPI Register Manual
www.ti.com
Table 20-24. MCSPI_SYSSTATUS
Address Offset
0x14
Physical Address
0x4809 8014
Instance
MCSPI1
0x4809 A014
MCSPI2
0x480B 8014
MCSPI3
0x480B A014
MCSPI4
Description
This register provides status information about the module excluding the interrupt status information
Type
R
Write Latency
Immediate
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
RESETDONE
Bits
Field Name
Description
Type
Reset
31:1
Reserved
Reserved for module specific status information.
R
0x00000000
Read returns 0
0
RESETDONE
Internal Reset Monitoring
R
0
0x0:
Internal module reset is on-going
0x1:
Reset completed
Table 20-25. Register Call Summary for Register MCSPI_SYSSTATUS
McSPI Basic Programming Model
•
•
McSPI Configuration and Operations Example
McSPI Register Manual
•
Table 20-26. MCSPI_IRQSTATUS
Address Offset
0x18
Physical Address
0x4809 8018
Instance
MCSPI1
0x4809 A018
MCSPI2
0x480B 8018
MCSPI3
0x480B A018
MCSPI4
Description
The interrupt status regroups all the status of the module internal events that can generate an interrupt
Type
RW
Write Latency
Immediate
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
WKS
EOW
Reserved
Reserved
Reserved
RX3_FULL
RX2_FULL
RX1_FULL
RX0_FULL
TX3_EMPTY
TX2_EMPTY
TX1_EMPTY
TX0_EMPTY
RX0_OVERFLOW
TX3_UNDERFLOW
TX2_UNDERFLOW
TX1_UNDERFLOW
TX0_UNDERFLOW
3036
Multichannel SPI
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated