Texas Instruments OMAP36 Series, Technical Reference Manual

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McSPI Register Manual
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Table 20-37. Register Call Summary for Register MCSPI_CHxCONF
McSPI Functional Interface
• Multichannel SPI Protocol and Data Format : [0] [1] [2] [3] [4] [5] [6] [7]
• Transfer Format : [8]
McSPI Functional Description
• Master Transmit-and-Receive Mode (Full Duplex) : [9]
• Master Transmit-Only Mode (Half Duplex) : [10]
• Master Receive-Only Mode (Half Duplex) : [11]
• Single-Channel Master Mode : [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23]
• Start Bit Mode : [24] [25] [26] [27]
• Chip-Select Timing Control : [28]
• Programmable SPI Clock (spim_clk) : [29] [30] [31] [32] [33] [34]
• Dedicated Resources : [35] [36] [37] [38] [39]
• Slave Transmit-and-Receive Mode : [40]
• Slave Transmit-Only Mode : [41]
• Slave Receive-Only Mode : [42]
• FIFO Buffer Management : [43] [44] [45]
• Buffer Almost Full : [46] [47]
• Buffer Almost Empty : [48] [49]
• Interrupt Events in Master Mode : [50] [51]
• Interrupt Events in Slave Mode : [52] [53]
• DMA Requests : [54] [55]
• Idle Mode : [56]
McSPI Basic Programming Model
• Transfer Procedures without FIFO : [57]
• McSPI Configuration and Operations Example : [58] [59] [60] [61] [62] [63] [64] [65] [66] [67]
• Transfer Procedures with FIFO : [68]
McSPI Register Manual
• McSPI Register Summary : [69]
• McSPI Register Description : [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] [80] [81]
Table 20-38. MCSPI_CHxSTAT
Address Offset 0x30 + (0x14 * x) Index x= 0 to 3 for MCSPI1.
x= 0 to 1 for MCSPI2 and MCSPI3.
x= 0 for MCSPI4.
Physical Address 0x4809 8030 + (0x14 * x) Instance MCSPI1
0x4809 A030 + (0x14 * x) MCSPI2
0x480B 8030 + (0x14 * x) MCSPI3
0x480B A030 + (0x14 * x) MCSPI4
Description This register provides status information about MCSPI_TXx and MCSPI_RXx registers of channel x.
Type R
Write Latency Immediate
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
TXS
EOT RXS
TXFFF TXFFE
RXFFF RXFFE
Bits Field Name Description Type Reset
31:7 Reserved Read returns 0s. R 0x00000000
6 RXFFF Channel x FIFO Receive Buffer Full Status R 0x0
Read 0x0: FIFO Receive Buffer is not full
Read 0x1: FIFO Receive Buffer is full
5 RXFFE Channel x FIFO Receive Buffer Empty Status R 0x0
3048 Multichannel SPI SWPU177N – December 2009 – Revised November 2010
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