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McSPI Basic Programming Model
4. Write 0x3 in the SPI1.MCSPI_CH1CONF[11:7] WL field.
5. Set the SPI1.MCSPI_CH1CONF[6] EPOL bit to 0 for spi1_cs1 activated high during the active state.
6. Set the SPI1.MCSPI_CH1CONF[1] POL bit to 1 for spi1_clk held low during the active state.
7. Set the SPI1.MCSPI_CH1CONF[0] PHA bit to 1 for data latched on even numbered edges of spi1_clk.
Clock Initialization and spi1_cs1 Enable
The SPI1.
[2] MS bit was set to 0 (providing the clock).
In master mode, the SPI must provide the clock and enable the channel:
8. Set the SPI1.MCSPI_CH0CTRL[0] EN bit to 0 to disable channel 0, and set the
SPI1.MCSPI_CH1CTRL[0] EN bit to 1 to enable channel 1.
NOTE:
Read and write operations for the second slave are identical to those for the first slave.
20.6.2.6.4.2 Write Operation
1. Write 1 to the SPI1.
[4] TX1_EMPTY bit to reset the status.
2. Write the command/address or data value in the SPI1.MCSPI_TX1 register to transmit the value.
3. If the SPI1.
[4] TX1_EMPTY bit is set to 1, write 1 to it and return to Step 2
(polling method).
20.6.2.6.4.3 Read Operation
1. Read the SPI1.
[6] RX1_FULL bit and if it is set to 1, go to Step 2.
2. If the SPI1.
[6] RX1_FULL bit is set to 1, write 1 to it and return to Step 1 (polling
method).
NOTE:
Write and read operations can be performed simultaneously.
20.6.3 Transfer Procedures with FIFO
In the subsections below, the transfer procedures are described with FIFO using
(
[27:28] FFER or/and FFEW = 1).
The MCSPI module allows the transfer of one or more words, according to different modes:
•
Master normal, master turbo, slave
•
Transmit-and-receive, transmit-only, receive-only
•
Write and read requests: Interrupts, DMA
For these flows, the host process contains the main process and the interrupt routine, which is called on
the IRQ signals or by an internal call if the module is used in polling mode.
20.6.3.1 Common Transfer Procedure
The common transfer sequence is the host sequence for a transfer of any type defined above.
In multichannel, only one channel can use the FIFO. Before enabling the FIFO for a channel (FFExW and
FFExR bits in the MCSPI_CHx_CONF register), the host must ensure that the FIFO is not enabled for
another channel, even if these channels are not used.
In transmit/receive mode, the FIFO can be enabled for write or read request only, without FIFO for the
other request.
In slave mode, only channel 0 only can be activated. The correct spim_csx line is chosen in the
MCSPI_CH0CONF register with the SPIENSLV bits.
The MCSPI module can start the transfer only when the first write request is released by writing the
register, even in receive-only mode (only one write request occurs in this case).
shows the main process of the common transfer sequence.
3025
SWPU177N – December 2009 – Revised November 2010
Multichannel SPI
Copyright © 2009–2010, Texas Instruments Incorporated
