Texas Instruments OMAP36 Series, Technical Reference Manual

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McSPI Register Manual
Table 20-42. MCSPI_TXx
Address Offset 0x38 + (0x14 * x) Index x= 0 to 3 for MCSPI1.
x= 0 to 1 for MCSPI2 and MCSPI3.
x= 0 for MCSPI4.
Physical Address 0x4809 8038 + (0x14 * x) Instance MCSPI1
0x4809 A038 + (0x14 * x) MCSPI2
0x480B 8038 + (0x14 * x) MCSPI3
0x480B A038 + (0x14 * x) MCSPI4
Description This register contains a single SPI word to transmit on the serial link, whatever SPI word length is.
Type RW
Write Latency Immediate
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDATA
Bits Field Name Description Type Reset
31:0 TDATA Channel 0 Data to transmit RW 0x00000000
Table 20-43. Register Call Summary for Register MCSPI_TXx
McSPI Functional Description
• Master Transmit-and-Receive Mode (Full Duplex) : [0] [1] [2] [3]
• Master Transmit-Only Mode (Half Duplex) : [4]
• Master Receive-Only Mode (Half Duplex) : [5] [6] [7] [8] [9]
• Single-Channel Master Mode : [10]
• Dedicated Resources : [11] [12] [13] [14] [15]
• Slave Transmit-and-Receive Mode : [16] [17]
• Slave Receive-Only Mode : [18] [19] [20]
• Interrupt Events in Master Mode : [21] [22] [23] [24] [25] [26] [27]
• Interrupt Events in Slave Mode : [28] [29] [30] [31] [32] [33]
• Interrupt-Driven Operation : [34]
• Polling : [35]
• DMA Requests : [36] [37]
McSPI Basic Programming Model
• McSPI Configuration and Operations Example : [38]
• Common Transfer Procedure : [39] [40]
McSPI Register Manual
• McSPI Register Summary : [41]
• McSPI Register Description : [42] [43] [44] [45] [46]
3051 SWPU177N – December 2009 – Revised November 2010 Multichannel SPI
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