Texas Instruments OMAP36 Series, Technical Reference Manual

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McSPI Functional Description
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20.5.5.1.2 TXx_UNDERFLOW
The event TXx_UNDERFLOW is activated when the channel is enabled and if the MCSPI_TXx register or
if the FIFO is empty (not updated with new data) when an external master device starts a data transfer
with the McSPI (transmit and receive).
The TXx_UNDERFLOW is a harmless warning in master mode.
To avoid having TXx_UNDERFLOW event at the beginning of a transmission, the event
TXx_UNDERFLOW is not activated when no data has been loaded into the
MCSPI_TXx register since
channel has been enabled. To avoid having TXx_UNDERFLOW event, the MCSPI_TXx register must be
loaded seldom.
The SPIm. MCSPI_IRQSTATUS TXx_UNDERFLOW interrupt status bit must be cleared for interrupt line
de-assertion (if event enable as interrupt source).
20.5.5.1.3 RXx_ FULL
The RXx_FULL event is activated when channel is enabled and MCSPI_RXx register becomes filled
(transient event). When FIFO buffer is enabled ( MCSPI_CHxCONF [28] FFER bit set to 1), the RXx_ FULL
is asserted as soon as the number of bytes holds in the FIFO to be read reaches the
MCSPI_XFERLEVEL[13:8] AFL threshold.
The MCSPI_RXx register must be read to remove the source of the interrupt; the MCSPI_IRQSTATUS
RXx_FULL interrupt status bit must be cleared for interrupt line deassertion (if the event is enabled as the
interrupt source).
When FIFO is enabled, no new RXx_FULL event will be asserted as soon as the MPU has not performed
AFL+1 reads into
MCSPI_RXx . It is the responsibility of MPU to perform the right number of reads.
20.5.5.1.4 End Of Word Count
The MCSPI_IRQSTATUS [17] EOW event (End Of Word count) is activated when channel is enabled and
configured to use the built-in FIFO. This interrupt is raised when the controller had performed the number
of transfer defined in the MCSPI_XFERLEVEL[31:16] WCNT bit field. If WCNT is set to 0x0000, the
counter is not enable and this interrupt is not generated.
The End of Word count interrupt also indicates that the SPI transfer is halt on channel using the FIFO
buffer as soon as MCSPI_XFERLEVEL[31:16] WCNT is not reloaded and the channel is not re-enabled.
The MCSPI_IRQSTATUS [17] EOW interrupt status bit must be cleared for interrupt line de-assertion (if
event enable as interrupt source).
20.5.5.2 Interrupt Events in Slave Mode
In slave mode, the interrupt events related to the MCSPI_TXx register state are TXx_EMPTY and
TXx_UNDERFLOW. The interrupt events related to the MCSPI_RXx register state are RXx_FULL and
RX0_OVERFLOW (channels 1, 2, and 3 do not have a receiver overflow status bit). See the
MCSPI_IRQSTATUS register.
20.5.5.2.1 TXx_EMPTY
The TXx_EMPTY event is activated when a channel is enabled and its MCSPI_TXx register is empty.
Enabling the channel automatically raises this event. If the FIFO buffer is enabled ( MCSPI_CHxCONF [27]
FFEW bit set to 1), the TXx_EMPTY event is asserted as soon as there is enough space in buffer to write
a number of byte defined by the MCSPI_XFERLEVEL[5:0] AEL bit field.
The MCSPI_TXx register must be loaded with data to remove the source of the interrupt; the
SPIm. MCSPI_IRQSTATUS TXx_EMPTY interrupt status bit must be cleared for interrupt line deassertion
(if the event is enabled as the interrupt source).
When FIFO is enabled, no new TXx_EMPTY event will be asserted as soon as the MPU has not
performed the number of write into the
MCSPI_TXx register defined by MCSPI_XFERLEVEL[5:0] AEL bit
field. It is the responsibility of the MPU to perform the right number of writes.
3006 Multichannel SPI SWPU177N – December 2009 – Revised November 2010
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