Texas Instruments OMAP36 Series, Technical Reference Manual

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McSPI Register Manual
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Table 20-44. MCSPI_RXx
Address Offset 0x3C + (0x14 * x) Index x= 0 to 3 for MCSPI1.
x= 0 to 1 for MCSPI2 and MCSPI3.
x= 0 for MCSPI4.
Physical Address 0x4809 803C + (0x14 * x) Instance MCSPI1
0x4809 A03C + (0x14 * x) MCSPI2
0x480B 803C + (0x14 * x) MCSPI3
0x480B A03C + (0x14 * x) MCSPI4
Description This register contains a single SPI word received through the serial link, what ever SPI word length is.
Type R
Write Latency Immediate
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA
Bits Field Name Description Type Reset
31:0 RDATA Channel 0 Received Data R 0x00000000
Table 20-45. Register Call Summary for Register MCSPI_RXx
McSPI Functional Description
• Master Transmit-and-Receive Mode (Full Duplex) : [0] [1]
• Master Transmit-Only Mode (Half Duplex) : [2] [3] [4]
• Master Receive-Only Mode (Half Duplex) : [5] [6]
• Single-Channel Master Mode : [7] [8] [9] [10]
• Dedicated Resources : [11] [12] [13]
• Slave Transmit-and-Receive Mode : [14]
• Slave Transmit-Only Mode : [15] [16]
• End of Transfer Management : [17]
• Interrupt Events in Master Mode : [18] [19] [20] [21]
• Interrupt Events in Slave Mode : [22] [23] [24] [25] [26] [27]
• Interrupt-Driven Operation : [28]
• Polling : [29]
• DMA Requests : [30]
• Idle Mode : [31]
McSPI Basic Programming Model
• McSPI Configuration and Operations Example : [32]
McSPI Register Manual
• McSPI Register Summary : [33]
• McSPI Register Description : [34] [35]
3052 Multichannel SPI SWPU177N – December 2009 – Revised November 2010
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