mcspi-013
spim_csx
spim_simo
spim_clk
Transmitter buffer
Shift register
Master
Control
Receiver register
Master SPI shift register
Initial
After 8 spim_clk
clock cycles
WordA
WordB
Slave SPI shift register
Initial
After 8
clock cycles
spim_clk
WordB
WordA
Control
Slave
Transmitter buffer
Shift register
spim_somi
Receiver register
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McSPI Functional Description
Figure 20-14. SPI Full-Duplex Transmission (Example)
20.5.2.3 Master Transmit-Only Mode (Half Duplex)
The master transmit-only mode prevents the MPU from reading the
register (minimizing data
movement) when only transmission is meaningful.
The master transmit-only mode is programmable per channel (the SPIm.
[13:12] TRM
field). Transmission starts only after data is loaded into the
register.
Rule 1 and Rule 2, defined in
, are applicable in this mode.
Rule 3, defined in
, is not applicable.
In master transmit-only mode, the
register state FULL does not prevent transmission and the
register is always overwritten with the new SPI word. This event is not significant when only
transmission is meaningful. Thus, the RX0_OVERFLOW bit in the SPIm.
register is
never set in this mode.
The hardware automatically disables the RX_FULL interrupt and the DMA read requests.
The transfer status is given by the SPIm.
[2] EOT bit.
20.5.2.4 Master Receive-Only Mode (Half Duplex)
The master receive mode prevents the MPU from refilling the
register (minimizing data
movement) when only reception is meaningful.
The master receive mode is programmable per channel (the SPIm.
[13:12] TRM field).
The master receive-only mode enables channel scheduling only on the empty state of the
register.
Rule 1 and Rule 3, defined in
, are applicable in this mode.
Rule 2, defined in
, is not applicable.
2993
SWPU177N – December 2009 – Revised November 2010
Multichannel SPI
Copyright © 2009–2010, Texas Instruments Incorporated