Texas Instruments OMAP36 Series, Technical Reference Manual

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McSPI Register Manual
Table 20-36. MCSPI_CHxCONF
Address Offset 0x2C + (0x14 * x) Index x= 0 to 3 for MCSPI1.
x= 0 to 1 for MCSPI2 and MCSPI3.
x= 0 for MCSPI4.
Physical Address 0x4809 802C + (0x14 * x) Instance MCSPI1
0x4809 A02C + (0x14 * x) MCSPI2
0x480B 802C + (0x14 * x) MCSPI3
0x480B A02C + (0x14 * x) MCSPI4
Description This register is dedicated to the configuration of the channel x.
Type RW
Write Latency Immediate
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCS IS TRM WL CLKD
SBE POL PHA
FFER DPE1 DPE0
EPOL CLKG
FFEW DMAR
DMAW
SBPOL
FORCE TURBO
Reserved Reserved
Bits Field Name Description Type Reset
31:30 Reserved Read returns 0s. RW 0x00
29 CLKG Clock divider granularity. This register defines the granularity of RW 0x0
channel clock divider: power of two or one clock cycle granularity.
When this bit is set, the
MCSPI_CHxCTRL [15:8] EXTCLK bit field
must be configured to reach a maximum of 4096 clock divider
ratio. Then the clock divider ratio is a concatenation of
MCSPI_CHxCONF [5:2] CLKD and EXTCLK values.
0x0: Clock granularity of power of two
0x1: One clock cycle ganularity
28 FFER FIFO enabled for Receive. Only one channel can have this bit RW 0x0
field set.
0x0: The buffer is not used to Receive data
0x1: The buffer is used to Receive data
27 FFEW FIFO enabled for Transmit. Only one channel can have this bit RW 0x0
field set.
0x0: The buffer is not used to Transmit data
0x1: The buffer is used to Transmit data
26:25 TCS Chip select time control RW 0x0
Defines the number of interface clock cycles between CS toggling
and first (or last) edge of SPI clock.
0x0: 0.5 clock cycle
0x1: 1.5 clock cycles
0x2: 2.5 clock cycles
0x3: 3.5 clock cycles
24 SBPOL Start bit polarity RW 0x0
0x0: Start bit polarity is held to 0 during SPI transfer.
0x1: Start bit polarity is held to 1 during SPI transfer.
23 SBE Start bit enable for SPI transfer RW 0x0
0x0: Default SPI transfer length as specified by WL bit field
0x1: Start bit D/CX added before SPI transfer. Polarity is
defined by
MCSPI_CHxCONF [SBPOL].
22:21 Reserved Write the reset value. Read returns the reset value. RW 0x0
20 FORCE Manual spim_csx assertion to keep spim_csx for channel x active RW 0x0
between SPI words (single channel master mode only). The
MCSPI_MODULCTRL [0] SINGLE bit must bit set to 1.
3045 SWPU177N – December 2009 – Revised November 2010 Multichannel SPI
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