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McSPI Functional Description
20.5.4.3 End of Transfer Management
When the FIFO buffer is enabled for a channel, the user shall previously configure in the
MCSPI_XFERLEVEL register the AEL and AFL levels and especially the MCSPI_XFERLEVEL[31:16]
WCNT bit field to define the number of SPI words to be transferred using the FIFO before enabling the
channel.
This counter allows the controller to stop the transfer correctly after a defined number of SPI word
transfers. If WNCT is set to 0x0000, the counter is not used and the user must stop the transfer manually
by disabling the channel, in this case the user does not know how many SPI transfers have been done.
For received words, software shall poll the CHxSTAT[5] RXFFE bit and read the
Receive
register to empty the FIFO buffer.
When the End Of Word count interrupt is generated (
[17] EOW bit set), the user can
disable the channel and poll the
[5] RXFFE bit to know it lasts SPI words in the FIFO
buffer and read them.
No new request will be asserted again as long as system has not performed the right number of write
accesses.
NOTE:
The status bit RXFFE shows only the FIFO status. The data received are stored not only in
the FIFO, but also in the shift register and MCSPI_RX register. Therefore, the FIFO can be
empty even after receiving two words.
20.5.5 Interrupts
Each channel can issue interrupt events.
Each interrupt event has status bits in the SPIm.
register (RXx_FULL,
TXx_UNDERFLOW, TXx_EMPTY, ...) with x = [0,3] that indicate if service is required. Each status bit has
an interrupt enable bit (a mask) in the SPIm.
register (RXx_FULL_ENABLE,
TXx_UNDERFLOW_ENABLE, TXx_EMPTY_ENABLE, ...).
When an interrupt occurs and a mask is later applied on it, the interrupt line is not asserted again, even if
the interrupt source is not serviced.
The McSPI supports interrupt-driven and polling operations.
20.5.5.1 Interrupt Events in Master Mode
In master mode, the interrupt events related to the
register state are TXx_EMPTY and
TXx_UNDERFLOW. The interrupt event related to the
register state is RXx_FULL.
20.5.5.1.1 TXx_EMPTY
The TXx_EMPTY event is activated when a channel is enabled and its
register is empty
(transient event). Enabling a channel automatically triggers this event, except in master receive-only mode
(see
, Master Receive-Only Mode). When the FIFO buffer is enabled
(
[27] FFEW bit set to 1), the
TXx_EMPTY bit is set as soon as
there is enough space in buffer to write a number of bytes defined by the MCSPI_XFERLEVEL[5:0] AEL
bit field.
The
register must be loaded with data to remove the source of the interrupt; the
SPIm.
TXx_EMPTY interrupt status bit must be cleared for interrupt line deassertion
(if the event is enabled as the interrupt source).
When FIFO is enabled, no new TXx_EMPTY event will be asserted as soon as the MPU has not
performed the number of write into the
register defined by MCSPI_XFERLEVEL[5:0] AEL bit
field. It is the responsibility of the MPU to perform the right number of writes.
3005
SWPU177N – December 2009 – Revised November 2010
Multichannel SPI
Copyright © 2009–2010, Texas Instruments Incorporated
