spim_clk (POL=0)
spim_clk (POL=1)
slave select
(spim_csx)
SPI shift clock
(SPICLKREF)
TCS=0.5
TCS=1.5
TCS=2.5
TCS=3.5
TCS=0.5
TCS=1.5
TCS=2.5
TCS=3.5
mcspi-016
Public Version
McSPI Functional Description
www.ti.com
20.5.2.5.3 Turbo Mode
The turbo mode improves the throughput of the SPI interface when a single channel is enabled by
allowing transfers until the shift register and the
register are full. The turbo mode is useful
(time savings) when a transfer exceeds two words. This mode is programmable per channel (via the
SPI1.
[9] TURBO bit).
When several channels are enabled, the TURBO bit has no effect and the channel access to the shift
registers remains as previously described.
In turbo mode, Rule 1 and Rule 2 applies, but Rule 3 does not (see
). An enabled channel
can be scheduled if its receive register is full (the SPIm.
[0]) RXS bit) at the time of the
shift-register assignment until the shift register is full.
The
register cannot be overwritten in turbo mode. Consequently, the
SPIm.
[3] RX0_OVERFLOW bit is never set in this mode.
20.5.2.6 Start Bit Mode
In start bit mode, an extended bit is added before the SPI word in order to indicate whether the next SPI
word must be handled as a command or as data. This feature is only available in master mode. The start
bit mode cannot be used at the same time as turbo mode and/or force spim_csx mode. In this case, only
one channel can be used; round-robin arbitration is not possible.
This mode is programmable per channel by setting the SPIm.
[23] SBE bit to 1. The
polarity of the extended bit is programmable per channel. When the SPIm.
[24] SBPOL
bit is set to 0, the SPI word must be handled as a command. When the SPIm.
[24]
SBPOL bit is set to 1, the SPI word must be handled as data. Moreover, start-bit polarity can be changed
dynamically during start bit transfer without disabling the channel for reconfiguration; in this case, users
must configure the SPIm.
[24] SBPOL bit before writing the SPI word to be transmitted
to the TX register.
20.5.2.7 Chip-Select Timing Control
The chip select timing control is only available in master mode with automatic chip select generation
(
[0] SINGLE bit field set to 0), to add a programmable delay between chip select
assertion and first clock edge, or chip select removal and last clock edge.
This mode is programmable per channel (the TCS bit of the SPIm.
register).
shows the chip-select SPIEN timing control.
Figure 20-17. Chip-Select SPIEN Timing Controls
2996
Multichannel SPI
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated