Public Version
McSPI Functional Description
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•
Read the SPIm.
register to identify which event occurred.
•
Read the
register that corresponds to the event to remove the source of an RXx_FULL
event or write into the
register that corresponds to the event to remove the source of a
TXx_EMPTY event. No action is required to remove the source of the WKS (wake-up), TXx_
UNDERFLOW, and RX0_OVERFLOW events.
•
Write 1 into the corresponding bit of the SPIm.
register to clear an interrupt status
and then release the interrupt line.
The interrupt status bit must always be reset after channel enabling and before events are enabled as
interrupt sources.
20.5.5.4 Polling
When the interrupt capability of an event is disabled in the SPIm.
register, the
interrupt line is not asserted, but the status bits in the SPIm.
register can be polled by
software to detect when the corresponding event occurs.
Once the expected event occurs:
•
RXx_FULL: To remove the source of the event, the MPU must read the corresponding
register.
•
TXx_EMPTY: To remove the source of the event, the MPU must write into the corresponding
register.
•
WKS (wake-up), TXx_UNDERFLOW, and RX0_OVERFLOW: No action is required to remove the
source of the event.
To clear an interrupt, set the corresponding status bit of the SPIm.
register to 1. This
does not affect the interrupt line state.
20.5.6 DMA Requests
The sDMA controller module manages DMA accesses. The sDMA controller advantage is to lower the
MPU charge for data transfers.
Each McSPI channel can issue DMA requests if they are enabled. There are two DMA request lines per
McSPI channel (one for read and one for write).
The DMA read request line is asserted when the McSPI channel is enabled and new data is available in
the receive register of the McSPI channel. A DMA read request can be individually masked with the
SPI1.
[15] DMAR bit. The DMA read request line is deasserted on read completion of
the
register of the McSPI channel.
The DMA write request line is asserted when the McSPI channel is enabled and the
register
of the McSPI channel is empty. A DMA write request can be individually masked with the
SPI1.
[14] DMAW bit. The DMA write request line is deasserted on load completion of
the
register of the channel.
20.5.7 Power Saving Management
Power consumption can be optimized by switching off internal clocks (interface and functional clock) when
there is no activity. The McSPI is compliant with the idle and wake-up system handshake protocol.
20.5.7.1 Normal Mode
In normal mode, internal SPI module clocks are automatically switched off (autogating) when there is no
activity in slave or master mode.
Autogating of the module interface clock and functional clock occurs when the following conditions are
met:
•
The SPIm.
[0] AUTOIDLE bit is set.
•
In master mode, there is no data to transmit or receive in all channels.
•
In slave mode, the McSPI is not selected by the external master and there are no register accesses.
3008
Multichannel SPI
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
