Public Version
McSPI Functional Description
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CAUTION
The PRCM module does not have a hardware means of reading the
CLOCKACTIVITY settings. Therefore, the software must ensure consistent
programming
between
the
CLOCKACTIVITY
and
the
PRCM
CORE_48M_FCLK and CORE_L4_ICLK control bits. If the McSPI is disabled in
both
the
CM_FCLKEN
and
CM_ICLKEN
PRCM
registers
while
CLOCKACTIVITY is set to 11, nothing prevents the PRCM module from
asserting its idle request, which is acknowledged regardless of the features
associated with the McSPI clocks. This can lead to unpredictable behavior.
20.5.7.2.1 Wake-Up Event in Smart-Idle Mode
The module wake-up feature is enabled when both the SPIm.
[2] ENAWAKEUP and
SPIm.
[0] WKEN bits are set. Wake-up capability is relevant only when the
module is configured in slave mode.
The module generates an asynchronous wake-up request to the system power manager to switch the
interface clock and the functional clock back. A wake-up is requested when channel 0 is enabled and an
asynchronous selection occurs on the spim.csx port associated with channel 0 (see the definition for the
SPIm.
SPIENSLV field (with x=0) in the register description table).
After the McSPI wake-up request, the system power manager must reactivate the interface clock:
•
Before the beginning of the second SPI word serialization when McSPI is in slave transmit-only mode
or in slave transmit-and-receive mode
•
Before the end of the second received SPI word in slave receive-only mode. To avoid data loss, the
first received SPI word must be read from the SPIm.
register (with x=0) before the
completion of the second SPI word serialization.
lists the supported cases in wake-up mode.
Table 20-15. Smart-Idle Mode and Wake-Up Capabilities
Mode
Interface Clock
SPI Clock Ref
Functionality
Wake-Up Event
Master
Must be
Must be
Full functionality, but the module does
No wake-up event
maintained
maintained
not generate a new interrupt or DMA
request until the system exits wake-up
mode.
Slave
Can be switched
Can be switched
An SPI word can be transmitted and/or
The module asynchronously sends a
off
off
received, but the module does not
wake-up request if an event on the
generate any new interrupts or DMA
spim_csx port associated to channel
requests until the system exits wake-up 0 is detected.
mode.
In wake-up mode, the interrupt and DMA request lines are no longer asserted.
Any access to the module in wake-up mode generates an error as long as the interface clock is alive.
20.5.7.2.2 Transitions From Smart-Idle Mode to Normal Mode
The McSPI detects the end of the wake period through the idle and wake-up hardware handshake
protocol.
The interrupt status register (the SPIm.
[16] WKS bit) is updated with the event
causing the wake-up; the wake-up event at the origin of the transition to the normal mode is converted to
its corresponding interrupt when enabled by the SPIm.
[16] WKE bit or the DMA
request.
Interrupts and wake-up events have independent enable/disable controls, accessible through the
SPIm.
and SPIm.
registers. Software must ensure the
overall consistency.
3010
Multichannel SPI
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
