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Display Subsystem Integration
To select the DSS1_ALWON_FCLK functional clock (the default clock selected after reset), write 0 in
the DSS.
[0] DISPC_CLK_SWITCH bit; to select the DSI1_PLL_FCLK functional clock,
write 1 in the DSS.
[0] DISPC_CLK_SWITCH bit.
NOTE:
The DSS1_ALWON_FCLK and DSI1_PLL_FCLK functional clocks must be active (the
PRCM.CM_FCLKEN_DSS[0] EN_DSS1 and DSI PLL programmed correctly) to switch from
one functional clock to another. The new functional clock is effective when the next vertical
blanking interval occurs. This is true only if the DSS.
[5] GOLCD bit is set
to 1.
Depending on the DPLL4 input clock frequency, the DSS1_ALWON_FCLK can be adjusted by setting the
PRCM.CM_CLKSEL_DSS[4:0] CLKSEL_DSS1 bit field.
•
DSI PLL functional clock (DSI_PLL_REFCLK)
The DSI PLL controller module can use either the DSS2_ALWON_FCLK (from PRCM) or the
PCLKFREE (from DISPC) functional clock. To select the DSS2_ALWON_FCLK functional clock
(default clock selected after reset), write 0 in the DSS.
DSI_PLL_CLKSEL bit; to select the PCLKFREE functional clock, write 1 in the
DSS.
[11] DSI_PLL_CLKSEL bit.
•
DSI protocol engine functional clocks (DSI_FCLK)
The DSI protocol engine can use either the DSS1_ALWON_FCLK (from PRCM) or the
DSI2_PLL_FCLK (from DSI PLL) functional clock. To select the DSS1_ALWON_FCLK functional clock
(default clock selected after reset), write 0 in the DSS.
[1] DSI_CLK_SWITCH bit; to
select the DSI2_PLL_FCLK functional clock, write 1 in the DSS.
DSI_CLK_SWITCH bit.
NOTE:
It is possible to switch between these two clocks, even when both of them are not active.
•
There are five clock domains in the DSI module:
–
Byte clock domain:
TxByteClkHS is generated from the bit clock and converted into a byte clock. The maximum
frequency is 112.5 MHz at nominal voltage (OPP100), and 100 MHz at low voltage (OPP50). It is
generated by the DSI complex I/O.
–
Functional clock domain
The DSI_FCLK is the functional clock for the DSI protocol engine module. The maximum frequency
is 173 MHz (nominal voltage) and 100 MHz (low voltage). It must always be equal to or higher than
the byte (TxByteClkHS), L4 interconnect (DSS_L4_ICLK), and video port (VP_CLK) clocks. The
software must configure the clocks correctly.
–
L4 interface clock domain
The DSS_L4_ICLK is used in the L4 interconnect port domain. The maximum frequency is 100
MHz at nominal voltage.
–
The video port domain
The pixel clock (PCLK) on the video port is used by the video port domain to capture the pixels
from the display controller. The maximum frequency of VP_CLK used as the functional clock for the
video port domain is 173 MHz at nominal voltage and 96 MHz at low voltage.
–
Serial Configuration Port (SCP) and Power Control (PWR) interfaces
The DSS_L4_ICLK is the functional clock.
NOTE:
•
There is no clock domain for RxClkEsc because it is used as an enable and not as a
clock by the DSI protocol engine module
•
The clock domains are asynchronous (except for L4 interconnect port and SCP/PWR
because both of them use DSS_L4_ICLK). The clocks used for the L4 interconnect port
and SCP/PWR interface must be balanced.
•
If video mode is used, the display controller functional clock must be generated using a
clock from the DSI PLL.
1621
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
