full
empty
MCSPI_XFERLEVEL[13:8]
AFL threshold
(in bytes)
t
MCSPI_IRQSTATUS
RXx_FULL bit
FIFO
state
MPU or DMA
read
SPI re
ce
p
tio
n
s
N
e
xt S
PI
re
ce
p
tio
n
RX0_OVERFLOW bit
mcspi-043
full
empty
Threshold (in bytes)
=
FIFO size
-
MCSPI_XFERLEVEL[5:0]
AEL
t
MCSPI_IRQSTATUS
TXx_EMPTY bit
FIFO
state
MPU or DMA
write
SPI tra
n
smissio
n
s
mcspi-044
Public Version
McSPI Functional Description
www.ti.com
Figure 20-24. Buffer Almost Full Level (AFL)
NOTE:
register bits are not available in DMA mode. In DMA mode, the
SPIm_DMA_RXx request is asserted on the same conditions than the
RXx_FULL flag.
20.5.4.2 Buffer Almost Empty
The MCSPI_XFERLEVEL[5:0] AEL bit field is needed when the buffer is used to transmit SPI word to a
slave (
[27] FFEW bit must be set to 1). It defines the Almost Empty buffer status. See
.
When FIFO pointer has not reached this level an interrupt or a DMA request is sent to the MPU to enable
system to write AEL+1 bytes to Transmit register. Be careful AEL+1 must correspond to a multiple value
of
[11:7] WL bit field.
When DMA is used, the request is de-asserted after the first Transmit register write.
No new request will be asserted again as long as system has not performed the right number of write
accesses.
Figure 20-25. Buffer Almost Empty Level (AEL)
NOTE:
register bits are not available in DMA mode. In DMA mode, the
SPIm_DMA_TXx request is asserted on the same conditions than the
TXx_EMPTY flag.
3004
Multichannel SPI
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
