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Display Subsystem Functional Description
value written in the register should be used instead for command and video modes. In case of
synchronization short packets for video mode, since the hardware generates the short packets without
using DSS.
registers. If the DSS.
[8] ECC_TX_EN
bit is set to 1, the ECC is calculated; otherwise, the value zero is used. The feature is used to generate
incorrect ECC for debug purpose and to ease the check for the link and peripheral error detection and
correction.
For the payload, the DSS.
registers are used. Each 32-bit
PAYLOAD data is written into the DSS.
register from the MPU
subsystem or system DMA. It is buffered to be able to send packets with higher rate than the L4
interconnect frequency can provide. The word count defined in the
DSS.
registers is used to determine the number of bytes to be sent
using the DSS.
registers. The write into the
registers is required before accessing the
register. The hardware must be able to extract the length of
the payload and be able to discard extra data sent using the DSS.
register. The hardware takes into account the write into the DSS.
register only if the VC is enabled otherwise the write is ignored by hardware.
In the case of pixels received on the video port, only the DSS.
register is used. The video port pixels are used for the payload. When the pixel data is coming from the
display controller video port, the DSI protocol can add a DCS command byte between the packet header
and pixel data by setting the DSS.
[24] DCS_CMD_ENABLE bit to 0x1. The value will be either
0x2c (write_memory_start) by setting the DSS.
[25] DCS_CMD_CODE bit to 0x1, or 0x3c
(write_memory_continue) by setting the DSS.
[25] DCS_CMD_CODE bit to 0x0.
When transmitting RGB 16-BPP data, the DSS.
[26] RGB565_ORDER bit must be set to 0x1 to
maintain the pixel byte order as in video mode .
A 2-line ping-pong buffer is implemented to allow the DSI protocol engine to store incoming pixels from the
display controller through the video port while sending the DSI formatted frame to the DSI_PHY. The
ping-pong buffer is supported in command mode, provided the size of the packet defined in the header
register is less than the size of each line buffer (768 *32 bits). If the size of the packet is greater than the
size of the line buffer, the ping-pong mechanism cannot be used (both lines are used as a single line).
The ping-pong buffer status can be checked by the
[14] PP_BUSY bit.
•
When PP_BUSY equals 1, the ping-pong buffer is active and the line buffers are not ready to receive
data; therefore, the user cannot update a new header.
•
When PP_BUSY equals 0, at least one line buffer is empty; therefore, the user can update a new
header. PP-BUSY is then set to 0x1. If both line buffers are empty, the user can write two headers,
one following the other. PP_BUSY remains at 0x0 after the first header is written, and is set to 0x1
after second header is written.
An IRQ is available to allow software to update header on events. The IRQ is enabled by setting the
[8] PP_BUSY_CHANGE_IRQ bit to 0x1, and its status is accessible on the
[8] PP_BUSY_CHANGE_IRQ bit.
7.4.3.3.3 Video + Command Modes
The two modes can be interlaced to send two DSI streams to two types of panels: Video or command
types. The number of concurrent video stream is limited to a single one. The number of concurrent
command mode streams is limited to 4 when there is no video stream and 3 otherwise. In case there is
one DSI stream using video mode, the command mode pixels must be provided only on the L4
interconnect.
7.4.3.3.4 Burst Modes
•
Frequency-burst mode The frequency-burst mode is used to reduce the high-speed (HS) period by
increasing the clock frequency on the DSI link. It allows in some case, the power consumption
reduction of the link. The non-HS period used typically to drive the main panel can be used to send
data to the secondary panel or to allow feedback (acknowledge) from the primary and secondary
panels. The DSI protocol engine needs to buffer a full line before sending the HS packets for the line.
A double buffering mechanism is required to be able to send a line while the following one is being
1665
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
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