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Device Initialization by ROM Code
Table 26-12. Software Booting Configuration Structure (continued)
Field
Size [bytes]
Description
0x07: XIP memory with wait monitoring
Third booting device
2
0x08: MMC/SD2 Hybrid connection
0x09 to 0x0F: Reserved
0x10: UART
Fourth booting device
2
0x11: HS USB
Others: Reserved
Padding
2
Reserved
Clock Settings
Section 2 key
4
Synchronization key for section 2: 0xCF00AA02
Section 2 size
4
Size of section 2: 0x00000048 (72)
Flags
4
Bit mask of various switches, active when set to 1:
Bit [0]: If 1, the clock configuration defined in this structure is applied.
Bit [1]: Reserved
Bit [2]: Perform clock configuration settings.
Bit [3]: Set and lock DPLL4 PER.
Bit [4]: Set and lock DPLL1 (MPU).
Bit [5]: Set and lock DPLL3 (CORE).
Bit [6]: Bypass DPLL4 before setting clocks.
Bit [7]: Bypass DPLL1 before setting clocks.
Bit [8]: Bypass DPLL3 before setting clocks.
Bits [24..31]: System clock ID
Must be set accordingly to the SYS.CLK:
0x01: 12 MHz
0x02: 13 MHz
0x03: 16.8 MHz
0x04: 19.2 MHz
0x05: 26 MHz
0x06: 38.4 MHz
Others: Reserved, must not be set
General Clock Settings
PRM_CLKSRC_CTRL
4
Register value
PRM_CLKSEL
4
Register value
CM_CLKSEL1_EMU
4
Register value
Clock Configuration
CM_CLKSEL_CORE
4
Register value
CM_CLKSEL_WKUP
4
Register value
DPLL3 (Core) Settings
CM_CLKEN_PLL
4
Register value
CM_AUTOIDLE_PLL
4
Register value
CM_CLKSEL1_PLL
4
Register value
DPLL4 (Peripheral) Settings
CM_CLKEN_PLL
4
Register value
CM_AUTOIDLE_PLL
4
Register value
CM_CLKSEL2_PLL
4
Register value
CM_CLKSEL3_PLL
4
Register value
DPLL1 (MPU) Settings
CM_CLKEN_PLL_MPU
4
Register value
CM_AUTOIDLE_PLL_MPU
4
Register value
CM_CLKSEL1_PLL_MPU
4
Register value
3531
SWPU177N – December 2009 – Revised November 2010
Initialization
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