Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Basic Programming Model
NOTE: The destination graphics transparency color key is available only to the overlay with which
the graphics pipeline is connected. The software must set the correct configuration of the
LCD and digital overlays.
NOTE: When the alpha blender is enabled, the destination transparency color key is not available
and the source transparency color key applies to the graphics pixels and not the video pixels.
When all of these fields are set to the appropriate values, set the DSS. DISPC_CONTROL [5] GOLCD bit to
indicate that all shadow registers of the pipelines connected to the LCD output are latched by the
hardware (only if the DSS.
DISPC_CONTROL [0] LCDENABLE bit is already set to 1). If the LCD output is
disabled, the new values will be updated when the DSS. DISPC_CONTROL [0] LCDENABLE bit will be set
to 1.
7.5.3.5.4 LCD TDM
The following fields define the multiple cycle output configuration:
• First cycle (the DSS. DISPC_DATA_CYCLEk (k=0) register)
• Second cycle (the DSS. DISPC_DATA_CYCLEk (k=1) register)
• Third cycle (the DSS. DISPC_DATA_CYCLEk (k=2) register)
• Enable (the DSS. DISPC_CONTROL [20] TDMENABLE bit)
• Parallel mode (the DSS. DISPC_CONTROL [22:21] TDMPARALLEMODE field)
• Cycle format (the DSS. DISPC_CONTROL [24:23] TDMCYCLEFORMAT field)
• Unused bits (the DSS. DISPC_CONTROL [26:25] TDMUNUSEDBITS field)
When all of these bit fields are set to the appropriate values, set the DSS. DISPC_CONTROL [5] GOLCD
bit to indicate that all shadow registers of the pipelines connected to the LCD output are latched by the
hardware (only if the DSS.
DISPC_CONTROL [0] LCDENABLE bit is already set to 1). If the LCD output is
disabled, the new values will be updated when the DSS. DISPC_CONTROL [0] LCDENABLE bit will be set
to 1.
7.5.3.5.5 LCD Spatial/Temporal Dithering
The following bit fields define the LCD spatial/temporal dithering configuration:
• Number of frames (the DSS. DISPC_CONTROL [31:30] SPATIALTEMPORALDITHERINGFRAMES bit
field) with:
– 0x0 Spatial only (default value)
– 0x1 S Temporal over two frames
– 0x2 S Temporal over four frames
– 0x3 Reserved
• Enable (the DSS. DISPC_CONTROL [7] SPATIALTEMPORALDITHERENABLE bit)
– 0x0 Disabled (default value)
– 0x1 Enabled
When all of these bit fields are set to the appropriate values, set the DSS. DISPC_CONTROL [5] GOLCD
bit to indicate that all shadow registers of the pipelines connected to the LCD output are latched by the
hardware (only if the DSS.
DISPC_CONTROL [0] LCDENABLE bit is already set to 1). If the LCD output is
disabled, the new values will be updated when the DSS. DISPC_CONTROL [0] LCDENABLE bit will be set
to 1.
7.5.3.5.6 LCD Color Phase Rotation
The following bit fields define the color phase rotation configuration:
• Enable (the DSS. DISPC_CONFIG [15] CPR bit)
– 0x0 Disabled (default value)
1733 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
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