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General-Purpose Timers
The values of the GPTi.
and GPTi.
registers are calculated using the following formula:
•
Positive increment value = ( (INTEGER[ Fclk * Ttick] + 1) * 1e6) - (Fclk * Ttick * 1e6)
•
Negative increment value = (INTEGER[ Fclk * Ttick] * 1e6) - (Fclk * Ttick * 1e6)
NOTE:
Fclk clock frequency (kHz)
Ttick tick period (ms)
The timer overflow counter register (GPTi.
) and the timer overflow wrapping register (GPTi.
are used to filter interrupts. When the timer overflows, it increments the 24-bit
register. When the
24-bit
register values match the value in the 24-bit
register and the timer overflow is
asserted, the
register is reset and an interrupt is generated to the
register.
With the conversion block in reset state (the positive increment register, negative increment register, and
counter value register are zeroed), the programming model and the behavior of GPTIMER1, GPTIMER2,
and GPTIMER10 remain unchanged.
For 1-ms tick with a 32,768-Hz clock:
•
GPTi.
[31:0] POSITIVE_INC_VALUE = 232000
•
GPTi.
[31:0] NEGATIVE_INC_VALUE = -768000
•
GPTi.
[31:0] LOAD_VALUE = 0xFFFFFFE0
NOTE:
Any value of the tick period can be generated with the appropriate value of the GPTi.
registers.
By default, the GPTi.
, GPTi.
, GPTi.
, and GPTi.
registers
and the associated logic are in reset mode (all 0s) and have no action on the programming
model.
16.2.4.3 Capture Mode Functionality
When a transition is detected on the module input pin (EVENT_CAPTURE), the timer value in the
GPTi.
register can be captured and saved in the GPTi.
or GPTi.
register function of
the mode selected in the GPTi.
[13] CAPT_MODE bit. The edge detection circuitry monitors
transitions on the input pin (EVENT_CAPTURE).
The rising edge, falling edge, or both, can be selected in the GPTi.
[9:8] TCM field to trigger the timer
counter capture. The module sets the GPTi.
[2] TCAR_IT_FLAG bit when an active edge is detected,
and at the same time, the counter value GPTi.
is stored in timer capture register GPTi.
or
, as follows:
•
If the GPTi.
[13] CAPT_MODE bit is 0, then on the first enabled capture event the value of the
counter register is saved in the GPTi.
register, and all the next events are ignored (no update
on the GPTi.
register and no interrupt triggering) until the detection logic is reset or the
GPTi.
[2] TCAR_IT_FLAG bit is cleared by writing 1 in it.
•
If the GPTi.
[13] CAPT_MODE bit is 1, then on the first enabled capture event the value of the
counter register is saved in the GPTi.
register, and on the second enabled capture event, the
value of the counter register is saved in the GPTi.
register. If a capture interrupt is enabled, the
interrupt triggers on the second event capture. All other events are ignored (no update on
GPTi.
and no interrupt triggering) until the detection logic is reset or GPTi.
TCAR_IT_FLAG bit is cleared by writing 1 in it. This mechanism is useful for period calculation of a
clock, if that clock is connected to the EVENT_CAPTURE input pin.
The edge detection logic is reset (a new capture is enabled) when the active capture interrupt is servedthe
GPTi.
[2] TCAR_IT_FLAG bit (previously 1) is cleared by writing 1 to it or when the edge detection
mode bits (the GPTi.
[9:8] TCM field) are changed from no-capture mode detection to any other
mode. The timer functional clock (input to prescaler) is used to sample the input pin (EVENT_CAPTURE).
An input negative or positive pulse can be detected when the pulse time is greater than the functional
clock period. An interrupt is issued on edge detection if the capture interrupt enable bit is set in the
GPTi.
[2] TCAR_IT_ENA bit. See the examples in
and
.
2717
SWPU177N – December 2009 – Revised November 2010
Timers
Copyright © 2009–2010, Texas Instruments Incorporated
