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High-Speed USB OTG Controller
This enhanced idle control allows clocks to be activated/deactivated safely without complex software
intervention. In both cases, the high-speed USB controller power management is applied only to the
interface clock domain. The USB functional clock (60 MHz), USBHS_FCLK, is controlled by the
transceiver and is responsible only for a very small percentage of the module overall power consumption.
The high-speed USB controller has both master (initiator) and slave (target) interfaces.
•
As an initiator, the high-speed USB controller implements the standby handshake protocol to inform
the PRCM module when it enters standby mode and does not generate traffic on the interconnect.
•
As a target, the high-speed USB controller implements the IDLE handshake protocol to allow the
PRCM module requiring it to enter idle mode.
22.1.3.1.3.2 System Power Management
Master Interface Power Management
The high-speed USB controller can choose to go to standby mode, in which case it stops generating
transactions on the interconnect. The module standby leads the PRCM to disable the USB clocks to save
power.
The high-speed USB controller has a MSTANDBY handshake mechanism with the PRCM module (see
The module is ready to enter standby mode (indicated by the MSTANDBY signal to the PRCM asserted)
when there is no USB activity and the module is idle. It means the following:
•
The module is committed not to start any new transaction on its master interface.
•
The module is idle and, therefore, the power manager can start the procedure to turn off the interface
clock, if needed. This procedure must be implemented using the slave power-management protocol.
The handshake mechanism lets the module to go to standby state based on the
USBOTG.
[13:12] MIDLEMODE field.
•
Smart standby
The high-speed USB controller is configured in smart-standby mode
(USBOTG.
[13:12] MIDLEMODE field = 0x2). The module is ready to enter standby
mode (MSTANDBY is asserted) when there is no more activity on the USB master interface of the
interconnect. MSTANDBY is asserted when the module is idle and deasserted when the module is
activated by either an external USB event or an appropriate register access. The module then waits for
MWAIT deassertion before a DMA transfer is started.
•
Force standby
The high-speed USB controller is configured in force-standby mode
(USBOTG.
[13:12] MIDLEMODE field = 0x0).
–
When the high-speed USB controller operates as a host: The USBOTG.POWER[1]
SUSPENDMODE bit is set to 1 to bring the module to low-power mode (suspend mode). After this
setting, the high-speed USB controller waits for its idle state. The USBOTG.
ENABLEFORCE bit must be set to 1 to assert MSTANDBY. Similarly, to release the MSTANDBY
signal, an appropriate register access must be applied, which can be either of the following two
cases:
•
Remote wakeup causes a RESUME interrupt
•
Set the USBOTG.POWER[3] RESET bit to 1.
•
Write 0 to the USBOTG.
[0] ENABLEFORCE bit.
OR
•
Set the USBOTG.POWER[3] RESET bit to 1.
•
Write 0 to the USBOTG.
[0] ENABLEFORCE bit.
–
When the high-speed USB controller operates as a peripheral: When the USB bus is idle for 3 ms,
a SUSPEND interrupt is generated by the high-speed USB controller. The
USBOTG.
[0] ENABLEFORCE bit must be set to 1 to enable the MSTANDBY
signal. The high-speed USB controller then asserts MSTANDBY. Similarly, to release the
MSTANDBY signal, an appropriate register access must be applied, which can be either of the
following two cases:
3217
SWPU177N – December 2009 – Revised November 2010
High-Speed USB Host Subsystem and High-Speed USB OTG Controller
Copyright © 2009–2010, Texas Instruments Incorporated
