1
0
1
1
0
1
0
1
1
0
0
0
0
1
1
i2ci_scl
Data from device 1
Data from device 2
Device 1 loses
arbitration and
switches off
i2c _sda
i
(where i = 1, 2, 3)
i2c-009
WAIT
state
Start high
period
Clock from device 1
Clock from device 2
i2c _scl
i
(where i = 1, 2, 3)
i2c-010
Public Version
HS I
2
C Environment
www.ti.com
17.2.1.3.9 HS I
2
C Bus Arbitration
If two or more master transmitters start a transmission on the same bus simultaneously, an arbitration
procedure is invoked. This arbitration procedure uses the data presented on the serial bus by the
competing transmitters. When a transmitter senses that a high signal it has presented on the bus has
been overruled by a low signal, it switches to slave receiver mode, sets the arbitration lost flag (the
I2Ci.
[0] AL bit), and generates the arbitration lost interrupt.
shows arbitration
between two devices. The arbitration procedure gives priority to the device that transmits the serial data
stream with the lowest binary value. If two or more devices send identical first bytes, arbitration continues
on the subsequent bytes.
Figure 17-9. HS I
2
C Arbitration Between Master Transmitters
17.2.1.3.10 HS I
2
C Clock Generation and Synchronization
Under normal conditions, only one master device generates clock signal i2ci_scl. During arbitration,
however, there are two or more master devices, and the clock must be synchronized so that the data
output can be compared. The wired-AND property of the clock line means that the device that first
generates a low period of the clock line overrules the other devices. At this high-low transition, the clock
generators of the other devices are forced to start generating their own low periods. The clock line is then
held low by the device with the longest low period, while the other devices that finish their low periods
must wait for the clock line to be released before starting their high periods. A synchronized signal on the
clock line is thus obtained, where the slowest device determines the length of the low period and the
fastest device determines the length of the high period.
If a device pulls down the clock line for a longer time, all clock generators must enter the WAIT state. In
this way, a slave can slow down a fast master, and the slow device can create enough time to store a
received byte or prepare a byte to be transmitted.
shows clock synchronization.
Figure 17-10. HS I
2
C Synchronization of I
2
C Clock Generators
17.2.2 HS I
2
C in SCCB Mode
The SCCB is a 3-wire serial bus developed by Omnivision Technologies, Inc. The SCCB can also operate
in a modified 2-wire serial mode. For details, see the SCCB specifications version 2.1 document at
http://www.ovt.com/.
2774
SWPU177N – December 2009 – Revised November 2010
Multimaster High-Speed I
2
C Controller
Copyright © 2009–2010, Texas Instruments Incorporated
