prcm-085
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Start
Module functional
clock is running
Clear coresponding CM_FCLKEN1_<domain>
EN_<module> bit to 0
Yes
Module
functional clock
is gated
Are the Clock domain
Idle Condition*
No
Module IDLE mode?
Forced-idle
Smart-idle
Module functional clock
can be gated?
Test the module functional
clock <module>.
<module>_SYSC [9:8]
CLOCKACTIVITY bit field
Yes
No
End
Use internal
source clock?
Start
Use DPLL4/5
(peripheral)?
Select external source clock sys_altclk
for the selectable source functional clocks
(54MHz clock, 48M_FCLK)
Select DPLL 4/5 clocks as the
selectable source functional clocks
( 54MHz/ 48MHz )
Yes
No
Are the source clock
selectable?
Select the source clock
CM_CLKSEL_<domain>
Yes
No
Set corresponding CM_FCLKEN1_<domain>
EN_<module> bit to 1
Set the output clock divider for
120M_FCLK/ 96M_FCLK
No
Yes
Module functional
clock is running
End
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Configure M and N values of the
DPLL4/5, depending on the desired
clock frequency for all functional
clocks
No-idle
The
Software must ensure
coherence between
module idle state, clock
activity bit test, and
clock gating request.
Hardware test
Module power domain is ON
Module functional clock is gated
Satisfied?
* Clock domain Idle conditions are:
a. No other module sharing the same clock domain needs the clock.
(All modules of the clock domain are idled)
b. No wake-up event.
Public Version
www.ti.com
PRCM Basic Programming Model
The functional clock is enabled or disabled by writing the dedicated bit in the
CM_FCLKEN_<domain_name> register. This bit has a direct effect on the clock activity:
•
The functional clock is turned on if the bit is enabled and the clock is not yet active.
•
The functional clock is turned off if the bit is disabled and the clock is not required by any other
module.
Figure 3-90. Functional Clock Basic Programming Model
The functional clock must be disabled before switching or scaling its source clock. This means that all the
modules using the particular functional clock must not be active during clock switching. To switch a source
clock, perform the following sequence:
1. Disable the functional clock by setting the CM_FCLKEN_<power domain>EN_<module> bits to 0.
2. Modify the CM_CLKSEL_<power domain>CLKSEL_<clock> bits to select the new clock source or
clock divider.
3. Enable the functional clock by setting the CM_FCLKEN_<power domain>EN_<module> bits to 1.
The timing diagram in
is a generic example of this sequencing for a functional clock (CLK1).
The source clock can be switched between source clock 1 and source clock 2 using the
CM_CLKSEL_DOM.CLKSEL_CLK1 bit (source clock 1 is selected when the bit is set to 0; otherwise,
source clock 2 is selected). CLK1 can be requested by two modules, M1 and M2. The
CM_FCLKEN_DOM.EN_M1 and CM_FCLKEN_DOM.EN_M2 bits control the functional clock enable for
the two modules.
NOTE:
The activation or deactivation of the clock is implementation-dependent, not one cycle of the
source clock, as shown in
425
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated
