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Display Subsystem Register Manual
Bits
Field Name
Description
Type
Reset
31:20
VBP
Vertical back porch
RW
0x00
Encoded value (from 0 to 4095) to specify the number of line clock
periods to add to the beginning of a frame before the first set of pixels is
output to the display.
19:8
VFP
Vertical front porch
RW
0x00
Encoded value (from 0 to 4095) to specify the number of line clock
periods to add to the end of each frame.
7:0
VSW
Vertical synchronization pulse width
RW
0x00
In active mode, encoded value (from 1 to 256) to specify the number of
line clock periods (program to value minus one) to pulse the frame clock
(VSYNC) pin at the end of each frame after the end of frame wait (VFP)
period elapses. Frame clock uses as VSYNC signal in active mode.
In passive mode, encoded value (from 1 to 256) to specify the number of
extra line clock periods (program to value minus one) to insert after the
vertical front porch (VFP) period has elapsed.
Table 7-163. Register Call Summary for Register DISPC_TIMING_V
Display Subsystem Environment
•
Display Subsystem Basic Programming Model
•
Display Controller Basic Programming Model
:
•
LCD-Specific Control Registers
•
:
Display Subsystem Use Cases and Tips
•
Vertical and Horizontal Timings
:
•
Configure DISPC Timing, Window, and Color
:
Display Subsystem Register Manual
•
Display Controller Register Mapping Summary
:
Table 7-164. DISPC_POL_FREQ
Address Offset
0x06C
Physical address
0x4805 046C
Instance
DISC
Description
The register configures the signal configuration.
Shadow register, updated on VFP start period
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
ACBI
ACB
RF
IVS
IPC
IHS
IEO
ONOFF
Bits
Field Name
Description
Type
Reset
31:18
Reserved
Write 0s for future compatibility.
RW
0x0000
Read returns 0
17
ONOFF
HSYNC/VSYNC Pixel clock Control On/Off
RW
0
0x0:
HSYNC and VSYNC are driven on opposite edges of pixel clock
than pixel data
0x1:
HSYNC and VSYNC are driven according to bit 16
16
RF
Program HSYNC/VSYNC Rise or Fall
RW
0
0x0:
HSYNC and VSYNC are driven on falling edge of pixel clock (if
bit 17 set to 1)
0x1:
HSYNC and VSYNC are driven on the rising edge of pixel clock
(if bit 17 set to 1)
15
IEO
Invert output enable
RW
0
0x0:
Ac-bias is active high (active display mode)
1839
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated