f ps =
[(Hsw + 1) + (H p + 1) + 240 + (Hbp + 1)] x [(Vsw + 1) + V p + 320 + Vbp)] x (PCLK)
f
f
1
dss-E123
dss-124
1 frame
VSYNC
Vsw = 2
… ………
HSYNC
Vfp = 9
320H
Vbp = 6
1H
HSYNC
(zoom)
PCLK
Hsw = 2
Hfp = 3
240 PCLK
Hbp = 1
16 bits of data are sent to
the LCD every clock
during
this period.
Zoom in to view
1 Hsync cycle
……..
f ps =
[(2 + 1) + 4 + 240 + 2] x [(2 + 1) + 9 + 320 + 6] x 166.67 x 10
-9
1
dss-E125
Public Version
Display Subsystem Use Cases and Tips
www.ti.com
7.6.2.6
Vertical and Horizontal Timings
The vertical and horizontal timings and the pixel clock speed determine the number of frames updated per
second.
shows the timings for a 240 x 320 pixel QVGA LCD panel. If the pulse width (also
called blanking) and the front porch parameters are increased, more setup time is added before the data
is transferred. This additional time is beneficial for delaying the data transfer if the data is not ready
because of bandwidth limitations. Care must be taken to determine the fps when modifying these
parameters.
Use the following formula to determine the fps for a 240 x 320 QVGA LCD:
(22)
With:
•
Hsw: DSS.
[7:0] HSW bit field value
•
Hfp: DSS.
[19:8] HFP bit field value
•
Hbp: DSS.
[31:20] HBP bit field value
•
Vsw: DSS.
[7:0] VSW bit field value
•
Vfp: DSS.
[19:8] VFP bit field value
•
Vbp: DSS.
[31:20] VBP bit field value
•
PCLK: Pixel clock period
The horizontal (Hsw) and vertical (Vsw) pulse widths and the horizontal front (Hfp) and back (Hbp)
porches are increased by 1 because the value is programmed as the desired value minus 1.
Figure 7-152. QVGA LCD Timings
The fps for the example of 6-MHz pixel clock with the setting shown in
is as follows:
fps = 71.57Hz
(23)
1792
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated