Texas Instruments OMAP36 Series, Technical Reference Manual

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Display Subsystem Use Cases and Tips
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The unsigned integer value range is [0:1023]. The accumulator value indicates on which phase the
horizontal filtering starts. The value 0 indicates that the phase 0 is the first phase used by the hardware
to generate the first data
Table 7-76 lists the vertical/horizontal accumulator values and phases
Table 7-76. Vertical/Horizontal Accumulator Phase
Accumulator Value Phases
0 0
128 1
256 2
384 3
512 4
640 5
768 6
896 7
NOTE: For LCD output, the initial phase is always 0 (horizontal and vertical.) For TV output, the
vertical phases (odd and even) can be nonzero values.
7.6.1.3.5 Coefficients
• Vertical up/downsampling coefficients (DSS. DISPC_VIDn_FIR_COEF_HVi and
DSS. DISPC_VIDn_FIR _COEF_V)
The 3-tap vertical up/downsampling coefficients are defined in DSS. DISPC_VIDn_FIR_COEF_HVi
registers. There are eight registers for the eight phases with three coefficients for each of them so a
total of 24 programmable coefficients for the vertical up/downsampling block. Each register contains
two 8-bit signed coefficients and one 8-bit unsigned coefficient (central one).
In addition, there are 2-tap vertical up/downsampling coefficients defined in
DSS.
DISPC_VIDn_FIR_COEF_Vi registers. There are eight registers for the eight phases with two
coefficients for each of them so a total of 16 programmable coefficients for the vertical
up/downsampling block used in addition of the 3-tap registers defined above. Each register contains
two 8-bit signed coefficients (C
22
() and C
00
()).
In case of 5-tap configuration, both sets of registers, DSS. DISPC_VIDn_FIR_COEF_HVi and
DSS. DISPC_VIDn_FIR _COEF_V, are used. In case of 3-tap configuration, only one set of registers,
DSS. DISPC_VIDn_FIR _COEF_HV, is used.
• Horizontal up/downsampling coefficients (DSS. DISPC_VIDn_FIR_COEF_Hi and
DSS. DISPC_VIDn_FIR _COEF_HV)
The 5-tap horizontal up/downsampling coefficients are defined in DSS. DISPC_VIDn_FIR_COEF_Hi
and DSS. DISPC_VIDn_FIR_COEF_HVi registers. There are eight registers for the eight phases with
five coefficients for each register, for a total of 40 programmable coefficients for the horizontal
up/downsampling block.
Each DSS.
DISPC_VIDn_FIR_COEF_Hi register contains three 8-bit signed coefficients and one 8-bit
unsigned coefficient (central one), and each DSS. DISPC_VIDn_FIR_COEF_HVi contains one 8-bit
signed coefficient.
Table 7-77 through Table 7-82 give the programmable coefficients for the FIR up/downsampling filters
(Max-Fauque-Berthier method).
7.6.1.3.5.1 Up-Sampling
Table 7-77 gives the 24 coefficients to program the vertical upsampling (3-tap configuration).
1784 Display Subsystem SWPU177N – December 2009 – Revised November 2010
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