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SDMA Functional Description
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11.4.19.3 Descriptors
A transfer descriptor is a set of values that maps to a set of logical channel configuration registers. Such a
descriptor contains the parameters associated with a transfer profile (transfer size, source or destination
addresses, etc). Four different types of transfer descriptors are supported to optimize the memory size
required to store a long linked list, and to minimize MPU use to create and maintain the descriptor list.
A transfer descriptor is a list of 32-bit values. A descriptor must be 32-bit-aligned in memory. Only the 30
least-significant bits (LSBs) of the next-descriptor address pointer are updated from the descriptor, and the
DMA4 forces the 2 LSBs to 0 on the generation of the pointer address. The descriptor size, which is
variable, depends on the descriptor type and the Nxt_Dv and Nxt_Sv bit fields.
Transfer descriptor bit mapping is the same as DMA4 logical-channel configuration register bit mapping,
with the following exceptions:
•
Src_Element_index and Dst_Element_index are concatenated in the same 32-bit location.
•
(interrupt event mask)
•
CFN (frame number)
•
Bit fields:
–
P: Corresponds to the PAUSE_LINK_LIST bit:
•
When set to 1 in the descriptor, the channel is suspended when the descriptor load completes.
•
The user must not set this bit to 1 through the configuration port. Otherwise, behavior is
undefined.
•
When set to 0 (through configuration port) after pause, the linked-list channel resumes its
transfer (either descriptor load or data load).
–
B: Corresponds to the end-of-block enable bit (BLOCK_IE) of the
register. Valid only
for type 3. This value is don't care for descriptor types 1 and 2 where
is fully
specified.
–
Nxt_Dv, Nxt_Sv: Mapped in the
register. They indicate one of the following
possibilities:
•
Next descriptor contains an updated destination or source address.
•
Next descriptor does not update the source or destination address, but increments the last
source or destination address (from the end of the last transfer).
•
The next source address and/or destination address are the last valid ones in the configuration
memory. This means that the corresponding location in the configuration memory is not updated
(assuming that they were initialized at least once in the past). This is also called wrapping
addressing.
–
Next_Descriptor_Type: Specify the next descriptor type that corresponds to the
NEXT_DESCRIPTOR_TYPE bit field in the
register.
11.4.19.3.1 Type 1
A type 1 descriptor includes the overall channel configuration register value to be loaded (global registers
are not part of the type 1 descriptor). This descriptor is used primarily when major changes are required:
•
Channel read or write access profiles must be modified, for instance, for bursting and packing
(included in the
register).
•
Attach a new DMA request to the same channel or change the priority (included in the
register).
•
Enable solid or transparent color fill (included in the
and
registers).
•
Enable a channel link (included in the
register).
shows a type 1 descriptor.
2362
SDMA
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
