Texas Instruments OMAP36 Series, Technical Reference Manual

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CLK(R/X)
D(R/X)
Data delay 0
FS(R/X)
B7 B6 B5 B4 B3
D(R/X)
Data delay 1
B7 B6 B5 B4
D(R/X)
Data delay 2
B7 B6 B5
0-bit delay
1-bit delay
2-bit delay
mcbsp-052
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McBSP Basic Programming Model
If a dual-phase frame is selected (RPHASE=1), the frame length must be two words(one word for phase 1
plus the one word for phase 2). Others values must not be used.
The 7–bit RFRLEN1 field allows up to 128 words per phase when single-phase frame. See Table 21-26
below for a summary of how to calculate the frame length. This length corresponds to the number of
words or logical time slots or channels per frame-synchronization pulse.
Program the RFRLEN fields with [W - 1], where W represents the number of words per phase. For
example, to get a phase length of 128 words in phase 1, load 127 words into RFRLEN1.
Table 21-26. How to Calculate the Length of the Receive Frame
RPHASE RFRLEN1 RFRLEN2 Frame Length
0 0 ≤ RFRLEN1 ≤ 127 Don’t care (RFRLEN1) words
1 RFRLEN1 = 0 RFRLEN2 = 0 2 words
21.5.1.5.2.2.4 Set the Receive Reverse Mode
The McBSPi. MCBSPLP_RCR2_REG [4:3] RREVERSE bit field determines whether reverse (LSB first)
data transfer option is chosen for McBSP reception.
For further information about reverse mode, see Section 21.4.2.2 .
21.5.1.5.2.2.5 Set the Receive Data Delay
The McBSPi. MCBSPLP_RCR2_REG [1:0] RDATDLY bit field determines the length of the data delay for
the receive frame.
The start of a frame is defined by the first clock cycle in which frame synchronization is active. The
beginning of actual data reception or transmission with respect to the start of the frame can be delayed if
required. This delay is called data delay.
McBSPi. MCBSPLP_RCR2_REG [1:0] RDATDLY specifies the data delay for reception. The range of
programmable data delay is zero to two bit–clocks (RDATDLY=0b00–0b10), as shown in Figure 21-62
below. In this figure, the data transferred is an 8–bit value with bits labeled B7, B6, B5, and so on.
Typically a 1-bit delay is selected, because data often follows a 1–cycle active frame-synchronization
pulse.
Figure 21-62. Range of Programmable Data Delay
21.5.1.5.2.2.5.1 0-Bit Data Delay
Normally, a frame-synchronization pulse is detected or sampled with respect to an edge of internal serial
clock CLK(R/X). Thus, on the following cycle or later (depending on the data delay value), data may be
received or transmitted. However, in the case of 0–bit data delay, the data must be ready for reception
and/or transmission on the same serial clock cycle.
For reception, this problem is solved because receive data is sampled on the first falling edge of CLKR
3137 SWPU177N – December 2009 – Revised November 2010 Multi-Channel Buffered Serial Port
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