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Camera ISP Basic Programming Model
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6.5.12.4.2 Camera ISP CBUFF Status Checking
The event status can be checked through the CBUFFx_READY_IRQ, CBUFFx_INVALID_IRQ and
CBUFFx_OVR_IRQ bits in the
registers.
In addition to those status bits the circular buffer module provides read only access to the "current
window", "next window" and "CPU windows" indexes through the
register. The "CPU
window" index can for example be used by the processor to compute the address of the physical buffer.
Those indexes can also be used to evaluate latency margins.
6.5.12.5 Camera ISP CBUFF Register Accessibility During Frame Processing
All registers are Busy-writeable registers. These registers/fields can be read or written even if the module
is busy. Changes to the underlying settings takes place instantaneously. However the module behavior is
unpredictable when registers are changed during processing.
For correct operation software must follow the following steps:
•
Disable all accesses to the virtual space managed by CBUFFx. For example when the circular buffer
relocates data provided by the CCDC module SW must disable the CCDC module and check SBL
status registers to make sure there are no more outstanding transactions.
•
Disable circular buffer x by clearing the
[0] ENABLE bit.
•
Change the configuration.
•
Re-enable CBUFFx by setting the
[0] ENABLE bit.
6.5.12.6 Camera ISP CBUFF Operations
A CBUFFx_READY_IRQ event is generated each time processor can read data from the circular buffer.
Processor can clear the event when it starts processing the data to avoid masking of other events.
Processor can keep trace of the location on the data internally or use the circular buffer registers to
compute it.
The formula used for CBUFF1 is:
ADDR =
[3:0] CPUW x
+
(5)
Because of the functionality of the fragment, the formula used for CBUFF0 is:
ADDR -
[3:0] CPUW]
(6)
When processor is done with processing, it must free the buffer by setting the
[2] DONE
bit. Otherwise an overflow event may occur.
The circular buffer does not keep trace of end of frame events. They must be managed by the processor
using the end of frame event of the module that writes into the circular buffer. At the end of the frame
there may remain data in the "current write" and "next write" windows. For example, when the window size
is set to 8 lines and the image size is 20 lines only 2 window ready events are generated for a linear
addressing scheme. The remaining 4 lines can be read after the end of frame event.
No automatic reset of the CBUFF FSM occurs at the end of the camera ISP frame. Software must reset
the CBUFF by clearing the
[0] ENABLE bit when the frame has been completely
processed. A new frame can only start when
[0] ENABLE has been set.
6.5.13 Programming the Camera ISP Software Reset
The flow chart in
describes the steps to perform a software reset.
1300
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
