Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 1146 / 3738

Public Version
Camera ISP Integration
www.ti.com
Table 6-15. Camera ISP Interrupts (continued)
Event Mask Description
ISP_IRQ0STATUS [25] OVF_IRQ ISP_IRQ0ENABLE [25] OVF_IRQ Central-resource SBL overflow: triggered when
one of the buffers in the central-resource SBL
overflows
ISP_IRQ0STATUS [24] ISP_IRQ0ENABLE [24] RSZ_DONE_IRQ RESIZER module. Resizer processing-done
RSZ_DONE_IRQ event:
Triggered at the end of the frame when
processing is complete for the current frame. It
applies to one-shot and continuous modes.
ISP_IRQ0STATUS [21] CBUFF_IRQ ISP_IRQ0ENABLE [24] CBUFF_IRQ CBUFF module event. See CBUFF_IRQSTATUS
to know which interrupt it is.
ISP_IRQ0STATUS [20] ISP_IRQ0ENABLE [20] PRV_DONE_IRQ PREVIEW module: Processing-done event:
PRV_DONE_IRQ triggered at the end of the frame when processing
is complete for the current frame
ISP_IRQ0STATUS [19] ISP_IRQ0ENABLE [19] PRV_DONE_IRQ CCDC module. The prefetch error indicates when
CCDC_LSC_PREFETCH_ERROR the gain table was read too slowly from memory.
When this event is pending, the module goes into
transparent mode (output = input). Normal
operation can be resumed at the start of the next
frame after:
1) Clearing this event
2) Disabling the LSC module
3) Enabling it
ISP_IRQ0STATUS [18] ISP_IRQ0ENABLE [18] CCDC module. Indicates the current state of the
CCDC_LSC_PREFETCH_COMPLETE CCDC_LSC_PREFETCH_COMPLETED prefetch buffer. Can be used to start sending the
D data once the buffer is full to minimize the risk of
an underflow. This event is triggered when the
buffer contains 3 full paxel rows. It can be used to
minimize buffer underflow risks.
ISP_IRQ0STATUS [17] ISP_IRQ0ENABLE [17] CCDC_LSC_DONE CCDC module. The event is triggered when the
CCDC_LSC_DONE internal state of LSC toggles from BUSY to IDLE.
This happens when the LSC module has
completed processing the current frame.
ISP_IRQ0STATUS [16] ISP_IRQ0ENABLE [16] HIST_DONE_IRQ HIST module. Processing-done event: triggered at
HIST_DONE_IRQ the end of the frame when processing is complete
for the current frame
ISP_IRQ0STATUS [13] ISP_IRQ0ENABLE [13] H3A module. Auto exposure and auto white
H3A_AWB_DONE_IRQ H3A_AWB_DONE_IRQ balance processing done event:
Triggered at the end of the frame when
processing is complete for the current frame
ISP_IRQ0STATUS [12] ISP_IRQ0ENABLE [12] H3A_AF_DONE_IRQ H3A module. Autofocus processing-done event:
H3A_AF_DONE_IRQ triggered at the end of the frame when processing
is complete for the current frame
ISP_IRQ0STATUS [11] ISP_IRQ0ENABLE [11] CCDC_ERR_IRQ CCDC module. Faulty-pixel correction error:
CCDC_ERR_IRQ Faulty-pixel correction memory underflow.
Triggered to signal an error in the faulty-pixel
correction logic. The hardware did not have time
to read the faulty-pixel LUT from external memory
in time.
ISP_IRQ0STATUS [10] ISP_IRQ0ENABLE [10] CCDC_VD2_IRQ CCDC module. Programmable event 2: triggered
CCDC_VD2_IRQ by the falling edge on the cam_wen signal. This
event is not programmable.
ISP_IRQ0STATUS [9] ISP_IRQ0ENABLE [9] CCDC_VD1_IRQ CCDC module. Programmable event 1: triggered
CCDC_VD1_IRQ after a programmable number of horizontal lines is
received after a VS pulse
ISP_IRQ0STATUS [8] ISP_IRQ0ENABLE [8] CCDC_VD0_IRQ CCDC module. Programmable event 0: triggered
CCDC_VD0_IRQ after a programmable number of horizontal lines is
received after a VS pulse
ISP_IRQ0STATUS [7] CSI1_LC3_IRQ ISP_IRQ0ENABLE [4] CSI1_LC3_IRQ CSI1/CCP2B receiver module event. See
CCP2_LC23_IRQSTATUS to know which interrupt
it is.
1146 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated