Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
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5.5.9 iVLCD Registers
This section provides information about the iVLCD Module. Each register in the module is described
separately below.
5.5.9.1 iVLCD Register Mapping Summary
Table 5-525. iVLCD Register Mapping Summary
Register Name Type Register Width (Bits) Address Offset Physical Address
IVLCD_REVISION R 32 0x0000 0000 0x0008 0000
IVLCD_SYSCONFIG RW 32 0x0000 0010 0x0008 0010
IVLCD_SYSSTATUS R 32 0x0000 0014 0x0008 0014
IVLCD_CPUSTATUSREG R 32 0x0000 0AE8 0x0008 0AE8
IVLCD_CONFIGREG RW 32 0x0000 0AF4 0x0008 0AF4
IVLCD_COMMAND RW 32 0x0000 0FFC 0x0008 0FFC
VLCD_START RW 32 0x0000 1000 0x0008 1000
VLCD_MODE RW 32 0x0000 1004 0x0008 1004
VLCD_QIN_ADDR RW 32 0x0000 1008 0x0008 1008
VLCD_QOUT_ADDR RW 32 0x0000 100C 0x0008 100C
VLCD_IQIN_ADDR RW 32 0x0000 1010 0x0008 1010
VLCD_IQOUT_ADDR RW 32 0x0000 1014 0x0008 1014
VLCD_VLCDIN_ADDR RW 32 0x0000 1018 0x0008 1018
VLCD_VLCDOUT_ADDR RW 32 0x0000 101C 0x0008 101C
VLCD_DC_PREDj
(1)
RW 32 0x0000 1020 + (0x4*j) 0x0008 1020 + (0x4*j)
VLCD_IDC_PREDj
(1)
RW 32 0x0000 1038 + (0x4*j) 0x0008 1038 + (0x4*j)
VLCD_MPEG_INVQ RW 32 0x0000 1050 0x0008 1050
VLCD_MPEG_Q RW 32 0x0000 1054 0x0008 1054
VLCD_MPEG_DELTA_Q RW 32 0x0000 1058 0x0008 1058
VLCD_MPEG_DELTA_IQ RW 32 0x0000 105C 0x0008 105C
VLCD_MPEG_THRED RW 32 0x0000 1060 0x0008 1060
VLCD_MPEG_CBP RW 32 0x0000 1064 0x0008 1064
VLCD_LUMA_VECTOR RW 32 0x0000 1068 0x0008 1068
VLCD_HUFFTAB_DCY RW 32 0x0000 106C 0x0008 106C
VLCD_HUFFTAB_DCUV RW 32 0x0000 1070 0x0008 1070
VLCD_HUFFTAB_ACi
(2)
RW 32 0x0000 1074 + (0x4*i) 0x0008 1074 + (0x4*i)
VLCD_OFLEV_MAXiTAB RW 32 0x0000 107C + (0x4*i) 0x0008 107C + (0x4*i)
(2)
VLCD_CTLTAB_DCY RW 32 0x0000 1084 0x0008 1084
VLCD_CTLTAB_DCUV RW 32 0x0000 1088 0x0008 1088
VLCD_CTLTAB_ACi
(2)
RW 32 0x0000 108C + (0x4*i) 0x0008 108C + (0x4*i)
VLCD_OFFSET_DCY RW 32 0x0000 1094 0x0008 1094
VLCD_OFFSET_DCUV RW 32 0x0000 1098 0x0008 1098
VLCD_OFFSET_ACi
(2)
RW 32 0x0000 109C + (0x4*i) 0x0008 109C + (0x4*i)
VLCD_SYMTAB_DCY RW 32 0x0000 10A4 0x0008 10A4
VLCD_SYMTAB_DCUV RW 32 0x0000 10A8 0x0008 10A8
VLCD_SYMTAB_ACi
(2)
RW 32 0x0000 10AC + (0x4*i) 0x0008 10AC + (0x4*i)
VLCD_VLD_CTL RW 32 0x0000 10B4 0x0008 10B4
VLCD_VLD_NRBIT_DC RW 32 0x0000 10B8 0x0008 10B8
VLCD_VLD_NRBIT_AC RW 32 0x0000 10BC 0x0008 10BC
(1)
j = 0 to 5
(2)
i = 0 to 1
1004 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated