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Display Subsystem Basic Programming Model
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7.5.3.6.1 Digital Timings
The following bit fields define the timing information:
•
Data hold time (the DSS.
[19:17] HT bit field)
•
Logic clock divisor (the DSS.
[23:16] LCD bit field)
The 8-bit pixel clock divider (DSS.
[23:16]) bit field is used to select the logic clock
frequency. The LCD generates a range of pixel clock frequencies from FCK/1 to FCK/255, where FCK is
the input functional clock of the display controller.
7.5.3.6.2 Digital Frame/Field Size
The following bit fields define the field size (frame if progressive mode):
•
Number of lines per panel (the DSS.
[26:16] LPP bit field)
•
Number of pixels per line (the DSS.
[10:0] PPL bit field)
7.5.3.6.3 Digital Overlay
The following bit fields define the overlay attributes of the digital output:
•
Transparency color key (the DSS.
register (m=1))
•
Transparency color key enable (the DSS.
[12] TCKDIGENABLE bit)
•
Transparency color key selection between the destination graphics transparency color key and the
source video transparency color key (the DSS.
[13] TCKDIGSELECTION bit)
•
The default solid background color is defined in the DSS.
DEFAULTCOLOR bit field (i=1).
•
Alpha blender Enable (DSS.
[19] TVALPHABLENDERENABLE)
•
Global alpha blending values (DSS.
[23:16] VID2GLOBALALPHA and
DSS.
[7:0] GFXGLOBALALPHA). The value 0xFF corresponds to 100%
opaque and 0 to 100% transparent
NOTE:
The destination graphics transparency color key is available only to the overlay with which
the graphics pipeline is connected. The software must set the correct configuration of the
LCD and digital overlays.
NOTE:
When the alpha blender is enabled, the destination transparency color key is not available
and the source transparency color key applies to the graphics pixels and not the video pixels.
When this bit field is set to the appropriate values, set the DSS.
[6] GODIGITAL bit to
indicate that all shadow registers of the pipelines connected to the digital output are latched by the
hardware (only if the DSS.
[1] DIGITALENABLE bit is already set to 1). If the digital
output is disabled, the new values will be updated when the DSS.
[1] DIGITALENABLE
bit will be set to 1.
7.5.4 DSI Protocol Engine Basic Programming Model
This section describes the programming model of the DSI protocol engine.
7.5.4.1
Software Reset
The DSI protocol engine can be reset by software. This reset can be done for debug purposes or after a
protocol error and has the same effect as the hardware reset. The DSI protocol engine can be reset by
setting the DSS.
[1] SOFT_RESET bit to 1. The software can monitor the
[0] RESET_DONE status bit to wait for the completion of the reset procedure. If
after 5 reads, the DSS.
[0] RESET_DONE status bit still returns 0, it can be assumed
that an error occurred during the reset stage.
1738
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
