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McBSP Environment
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21.2.4.1 Words, Frames, and Phases Definitions
21.2.4.1.1 Words or Channels
The data bits are transferred (transmission or reception) in a group called a serial word or channel. The
number of bits in a word (length) is programmable via bits field (McBSPi.
RWDLEN1 field and McBSPi.
[7:5] RWDLEN2 field,
McBSPi.
[7:5] XWDLEN1 field and McBSPi.
XWDLEN2 field) and can be 8, 12, 16, 20, 24 or 32 bits (see
, Clocking and Framing
Data). The McBSP module uses clock signals to control the time for each bit transfer. Data are
sampled/driven on rising or falling edge of clock signals. This clock polarity is programmable via bits field
of pin-control register (McBSPi.
For more information, see
, Frame Phases (Dual-Phase Frame I2S Support).
21.2.4.1.2 Frames
One or more words (max 128) are transferred in a group called a frame. The McBSP module can transmit
/ receive a maximum of 128 words per frame, programmable via bits field of transmit and receive control
registers (McBSPi.
/McBSPi.
and
McBSPi.
/McBSPi.
). For more details, see
, Clocking and Framing Data.
All the words in a frame are sent in a continuous stream. However, there can be pauses between frame
transfers. The McBSP module uses frame-synchronization signals to determine when each frame is
received/transmitted. When a pulse occurs on a frame-synchronization signal, the McBSP module begins
receiving/transmitting a frame of data. When the next pulse occurs, the McBSP module receives/transmits
the next frame, and so on. Frame-synchronization pulse is active high or low. This pulse polarity is
programmable via bits field of pin-control register (McBSPi.
Each frame transfer can be delayed by 0, 1, or 2 clock cycles, depending on the value of bits for transmit
and receive control registers (McBSPi.
and McBSPi.
). For
more information, see
, Preventing Unexpected Receive Frame-sync Pulses and
, Preventing Unexpected Transmit Frame-sync Pulses.
21.2.4.1.3 Phases
The McBSP module allows configuring each frame to contain one or two phases. The McBSP module
supports dual phase frames to provide I2S fully compliant capabilities. These two phases represent left
and right channels of audio stereo signals.
The limitation on dual phase frame is that the number of words per phase must be set to one for both first
and second phase. But, the number of bits per word can be specified differently for each of the two
phases of a frame, allowing greater flexibility in structuring data transfers.
For example, software may define a frame composed of a first phase with one 12-bit word and a second
phase with one 16-bit word. This configuration allows the software to compose frames for custom
applications. For more details, see
, Frame Phases (Dual-Phase Frame I2S Support).
shows signal activity for two possible reception/transmission scenarios.
3064
Multi-Channel Buffered Serial Port
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
