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McBSP Functional Description
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21.4.2.4 Frame Phases (Dual-Phase Frame I2S Support)
The McBSP module allows you to configure each frame to contain one or two phases. The support for
dual-phase frames is required to provide I2S fully compliant capabilities (audio left and right
channels—stereo audio stream).
CAUTION
The limitation on dual-phase frame support is that the number of words per
phase must be set to 1 for both first and second phase. It is the only possible
value for word per frame when using the dual phase frame.
The number of bits per word can be specified differently for each of the two phases of a frame, allowing
greater flexibility in structuring data transfers. For example, a user might define a frame as consisting of
one phase containing one word of 16 bits, followed by a second phase consisting of one word of 32 bits.
This configuration allows the user to compose frames for custom applications such as I2S protocol.
21.4.2.4.1 Number of Phases, Words, and Bits per Frame
below shows which bit fields in the receive control registers (McBSPi.
and McBSPi.
) and in the transmit control registers
(McBSPi.
and McBSPi.
) determine the number of phases
per frame, the number of words per frame, and the number of bits per word for each phase, for both
receiver and transmitter. The maximum number of words per frame is limited to 2 when using dual-phase
frames (one word for each phase), and to 128 for a single-phase frame. The number of bits per word can
be 8, 12, 16, 20, 24, or 32 bits.
The following legend applies to the table:
•
RPHASE => McBSPi.
[15] RPHASE bit
•
XPHASE => McBSPi.
[15] XPHASE bit
•
RFRLEN1 => McBSPi.
[14:8] RFRLEN1 field
•
RFRLEN2 => McBSPi.
[14:8] RFRLEN2 field
•
XFRLEN1 => McBSPi.
[14:8] XFRLEN1 field
•
XFRLEN2 => McBSPi.
[14:8] XFRLEN2 field
•
RWDLEN1 => McBSPi.
[7:5] RWDLEN1 field
•
RWDLEN2 => McBSPi.
[7:5] RWDLEN2 field
•
XWDLEN1 => McBSPi.
[7:5] XWDLEN1 field
•
XWDLEN2 => McBSPi.
[7:5] XWDLEN2 field
Table 21-16. Phases, Words and Bits per Frame Control Bit
Operation
Number of phases
Words per frame set with
Bits per word set with
Reception
1 (RPHASE=0)
RFRLEN1
RWDLEN1
Reception
2 (RPHASE=1)
RFRLEN1=0x0 and RFRLEN2=0x0
RWDLEN1 for phase 1 RWDLEN2 for phase 2
Transmission
1 (XPHASE=0)
XFRLEN1
XWDLEN1
Transmission
2 (XPHASE=1)
XFRLEN1=0x0 and XFRLEN2=0x0
XWDLEN1 for phase 1 XWDLEN2 for phase 2
21.4.2.4.2 Single-Phase Frame Example
below shows an example of a single-phase data frame containing one 8-bit word. Because
the transfer is configured for one data bit delay, the data on the mcbspi_dx and mcbspi_dr pins are
available one clock cycle after FS(R/X) goes active. The following table shows the assumptions used in
the example of this figure.
3098
Multi-Channel Buffered Serial Port
SWPU177N – December 2009 – Revised November 2010
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