Public Version
McBSP Functional Description
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During transmission, XSR accepts new data from XB after a full serial word has been passed from XSR to
the mcbspi_dx pin.
In the example in
, an 8–bit word size was defined (see the transfer of the 8-bit word B).
21.4.2.3.3 Frames and Frame Synchronization
One or more words (up to 128) are transferred in a group called a frame. The software defines how many
words are in a frame by programming:
•
For the receiver: The McBSPi.
[14:8] RFRLEN1 field and the
[14:8] RFRLEN2 field.
•
For the transmitter: The McBSPi.
[14:8] XFRLEN1 field and the
[14:8] XFRLEN2 field.
The difference between these registers is explained to
. For the corresponding between
field value and words number, see
.
All the words in a frame are sent in a continuous stream. However, there can be pauses between frame
transfers. The McBSP module uses frame-synchronization signals (FSG) to determine when each frame is
received/transmitted. When a pulse occurs on a frame-synchronization signal, the McBSP module begins
receiving/transmitting a frame of data. When the next pulse occurs, the McBSP module receives/transmits
the next frame, and so on.
Pulses on the receive frame-synchronization (FSR_int) signal initiate frame transfers on mcbspi_dr. Pulses
on the transmit frame-sync (FSX_int) signal initiate frame transfers on mcbspi_dx. FSR_int or FSX_int
signals can be derived from a pin at the boundary of the McBSP module (mcbspi_fsr and mcbspi_fsx
respectively) or derived from inside the McBSP module (see
). The frame-sync source is
selected by programming the McBSPi.
[11] FSXM bit and the
McBSPi.
[10] FSRM bit respectively.
When the McBSPi.
[11] FSXM bit (transmitter frame-sync mode) is set to:
•
‘0’, FSX_int is derived from an external source and mcbspi_fsx is an input pin.
•
‘1’, FSX_int is determined by the McBSPi.
[12] FSGM bit and mcbspi_fsx is
an output pin.
For the McBSPi.
[10] FSRM bit (receiver frame-sync mode), is set to:
•
‘0’, FSR_int is generated by an external source and mcbspi_fsr is an input pin
•
‘1’, FSR_int is generated internally by sample rate generator. The mcbspi_fsx is an output pin except
when McBSPi.
[15] GSYNC bit = 0x1
In the example in
, a one-word frame is transferred when a frame-synchronization pulse
occurs. The polarities of FSR and FSX signals are programmable by bits on
McBSPi.
register.
The McBSPi.
[3] FSXP defines the transmit frame-sync polarity:
•
When set to ‘0’, frame-sync pulse FSX is active high
•
When set to ‘1’, frame-sync pulse FSX is active low
The McBSPi.
[2] FSRP defines the receive frame-sync polarity:
•
When set to ‘0’, frame-sync pulse FSR is active high
•
When set to ‘1’, frame-sync pulse FSR is active low
In McBSP operation, the inactive-to-active transition of the frame-synchronization signal indicates the start
of the next frame. For this reason, the frame-synchronization signal may be high for an arbitrary number of
clock cycles. Only after the signal is recognized to have gone inactive, and then active again, does the
next frame synchronization occur.
21.4.2.3.4 Detecting Frame-Synchronization Pulses, Even in Reset State
The McBSP module can generate receive and transmit interrupts to the MPU/IVA2.2 subsystems to
indicate specific events in the McBSP module. To facilitate detection of frame synchronization, these
interrupts can be sent in response to frame-synchronization pulses (see
for further details).
3096
Multi-Channel Buffered Serial Port
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated