Public Version
High-Speed USB Host Subsystem
www.ti.com
Bits
Field Name
Description
Type
Reset
7
RESERVED
Reserved
R
0x0
6
SUSPENDM
Active low PHY suspend: Puts the ULPI bus in Low
RW
0x0
Power Mode. Automatically set back to 1 upon Low
Power Mode exit.
Write 0x0: No effect on bit value
Write 0x1: Clear the bit to 0
5
RESET
Active high UTMI transceiver reset. Autocleared.
RW
0x0
Does not reset the ULPI interface or ULPI register set.
Write 0x0: No effect on bit value
Write 0x1: Clear the bit to 0
4:3
OPMODE
Select the required bit encoding style during transmit
RW
0x0
Write 0x0: No effect on bit value
Write 0x1: Clear the bit to 0
2
TERMSELECT
Controls the internal 1.5Kohms pull-up resistor and
RW
0x0
45ohms HS terminations. Control over bus resistors
changes depending on XcvrSelect, OpMode, DpPulldown
and DmPulldown.
Write 0x0: No effect on bit value
Write 0x1: Clear the bit to 0
1:0
XCVRSELECT
Select the required transceiver speed.
RW
0x0
Write 0x0: No effect on bit value
Write 0x1: Clear the bit to 0
Table 22-87. Register Call Summary for Register ULPI_FUNCTION_CTRL_CLR_i
High-Speed USB Host Subsystem
•
High-Speed USB Host Subsystem Register Summary
Table 22-88. ULPI_INTERFACE_CTRL_i
Address Offset
0x0000 0007 + (0x100 * i)
Index
i = 0 to 2
Physical Address
0x4806 2807 + (0x100 * i)
Instance
USBTLL
Description
Enables alternative interfaces and PHY features. Read/Write address.
Type
RW
7
6
5
4
3
2
1
0
RESERVED
AUTORESUME
RESERVED
CLOCKSUSPENDM
FSLSSERIALMODE_3PIN
FSLSSERIALMODE_6PIN
INTERFACE_PROTECT_DISABLE
Bits
Field Name
Description
Type
Reset
7
INTERFACE_PROTECT_DISAB
Controls circuitry built into the PHY for protecting the
RW
0x0
LE
ULPI interface when the link 3-states stp and data.
0x0: Enables the interface protect circuit
0x1: Disables the interface protect circuit
6:5
RESERVED
Reserved
R
0x0
3300
High-Speed USB Host Subsystem and High-Speed USB OTG Controller
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
