Public Version
www.ti.com
High-Speed USB Host Subsystem
22.2.6 High-Speed USB Host Subsystem Register Manual
22.2.6.1 USBTLL ULPI PHY-Side Register Space
Each ULPI port emulates a separate ULPI transceiver and as such gives access to a single set of ULPI
PHY-side registers, mapped in a separate ULPI register space as specified in the ULPI specification. The
ULPI protocol defines two register access methods: Immediate and extended.
•
The immediate space maps ULPI PHY-side registers in a 0x40- (64-) byte space (address is 6 bits
wide). All ULPI PHY-side registers implemented in the USBTLL implementation are in the immediate
space.
•
The extended register space maps all ULPI PHY-side registers in a 0x100- (256-) byte space (address
is 8 bits wide). The immediate space is remapped at the bottom of the extended space (that is, the
extended access method can be used to access any ULPI register).
An access is recognized as extended by first pointing to a reserved dummy address 0x2F
(EXTENDED_SET_ACCESS in
). Immediate-mode accesses to this address over the ULPI
interface are forbidden by the protocol and the USBTLL behavior is then undefined. Extended accesses to
this address have no effect.
Some physical registers are accessible at more than one address, where write accesses perform different
actions on the register value: (over-)write, set, clear. A read to any of the addresses returns the register
value. The names of the set and clear registers are the write name postfixed with respectively _SET and
_CLR. The register fields are described only once, at the write address (see
, USBTLL
Registers).
NOTE:
Some ULPI registers are cleared upon read.
22.2.6.2 L4-Core Interconnect Register Space
lists the base address and address space for the high-speed USB host subsystem.
Table 22-55. High-Speed USB Host Subsystem Instance Summary
Module Name
Base Address (hex)
Size
USBTLL
0x4806 2000
4096 bytes
UHH_config
0x4806 4000
1024 bytes
OHCI
0x4806 4400
1024 bytes
EHCI
0x4806 4800
1024 bytes
22.2.6.3 High-Speed USB Host Subsystem Register Summary
The USBTLL single L4-Core interconnect gives access to both the TLL control and status registers, and
the ULPI PHY-side registers.
lists all the USBTLL registers mapped by the L4-Core interconnect, for the maximum
8-channel configuration.
3285
SWPU177N – December 2009 – Revised November 2010
High-Speed USB Host Subsystem and High-Speed USB OTG Controller
Copyright © 2009–2010, Texas Instruments Incorporated
