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McBSP Register Manual
Table 21-62. MCBSPLP_SRGR1_REG
Address Offset
0x0000 002C
Physical Address
0x4807 402C
Instance
McBSP1
0x4809 602C
McBSP5
0x4902 202C
McBSP2
0x4902 402C
McBSP3
0x4902 602C
McBSP4
Description
McBSPLP SRG register 1
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
FWID
CLKGDV
Bits
Field Name
Description
Type
Reset
31:16
RESERVED
Read returns 0x0.
R
0x0000
15:8
FWID
Frame Width. This value + 1 determines the width of the
RW
0x00
frame-sync pulse, FSG, during its active period.
Range: 1 to 256 CLKG periods.
7:0
CLKGDV
Sample Rate Generator Clock Divider
RW
0x01
This value is used as the divide-down number to
generate the required SRG clock frequency.
Default value is 1.
Table 21-63. Register Call Summary for Register MCBSPLP_SRGR1_REG
McBSP Functional Description
•
•
:
•
Frame Sync Generation in the SRG
:
•
Synchronizing SRG Outputs to an External Clock
•
:
McBSP Basic Programming Model
•
McBSP Initialization Procedure
•
McBSP Register Manual
•
McBSP Register Mapping Summary
:
Table 21-64. MCBSPLP_MCR2_REG
Address Offset
0x0000 0030
Physical Address
0x4807 4030
Instance
McBSP1
0x4809 6030
McBSP5
0x4902 2030
McBSP2
0x4902 4030
McBSP3
0x4902 6030
McBSP4
Description
McBSPLP multi channel register 2
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
XMCM
XMCME
XPBBLK
XPABLK
RESERVED
3171
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated