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McBSP Functional Description
•
Otherwise, the software program the McBSPi.
[11:0] FPER field, and the
resulting frame-synchronization period is (FPER+1)CLKG cycles, where CLKG is the output clock of
the SRG. The range is from 1 to 4096 clock periods.
21.4.3.2.3 Keeping FSG Synchronized to an External Clock
When an external signal is selected to drive the SRG, the McBSPi.
[15] GSYNC
bit and the mcbspi_fsr pin can be used to configure the timing of FSG pulses.
McBSPi.
[15] GSYNC=1 ensures that the McBSP module and an external device
are dividing down the input clock with the same phase relationship.
If McBSPi.
[15] GSYNC=1, an inactive-to-active transition on the mcbspi_fsr pin
triggers a resynchronization of CLKG and generation of FSG.
21.4.3.3 Synchronizing SRG Outputs to an External Clock
The SRG can produce a clock signal (CLKG) and a FSG based on an input clock signal that is either the
interface clock signal (McBSPi_ICLK), or the CLKS signal (PRCM functional clock or mcbsp_clks), or a
signal at the mcbspi_clkr, or mcbspi_clkx pin. When an external clock (mcbsp_clks, or mcbspi_clkr, or
mcbspi_clkx) is selected to drive the SRG, the McBSPi.
[15] GSYNC bit and the
mcbspi_fsr pin can be used to control the timing of CLKG and the pulsing of FSG relative to the chosen
input clock. Make GSYNC=1 so that the McBSP module and an external device divide down the input
clock with the same phase relationship.
If the McBSPi.
[15] GSYNC bit=1:
•
An inactive-to-active transition on the mcbspi_fsr pin triggers a resynchronization of CLKG signal and a
pulsing of FSG signal.
•
CLKG signal always begins with a high state after synchronization.
•
FSR signal is always detected at the same edge of the input clock signal that generates CLKG signal,
no matter how long the FSR pulse is.
•
The McBSPi.
[11:0] FPER field are ignored because the
frame-synchronization period on FSG is determined by the arrival of the next frame-synchronization
pulse on the mcbspi_fsr pin.
If the McBSPi.
[15] GSYNC bit=0, CLKG signal runs freely and is not
resynchronized, and the frame-synchronization period on FSG signal is determined by
McBSPi.
[11:0] FPER field.
21.4.3.3.1 Operating the Transmitter Synchronously with the Receiver
When the McBSPi.
[15] GSYNC bit = 1, the transmitter can operate
synchronously with the receiver, provided that the FSX signal is programmed to be driven by FSG signal
(McBSPi.
[11] FSXM = 1). If
the FSR input signal has appropriate timing so that it can be sampled by the falling edge of CLKG signal,
it can be used, instead, by setting McBSPi.
[11] FSXM=0 and connecting FSR
signal to FSX externally.
The SRG clock drives the transmit and receive clocking (McBSPi.
[8] CLKRM bit
and McBSPi.
[9] CLKXM bit are set to 1). Therefore, the CLK(R/X) pin must not be
driven by any other driving source.
21.4.3.3.2 Synchronization Examples
and
show the clock and frame-synchronization operation with various polarities
of CLKS (the chosen input clock) and FSR signals. These figures assume
McBSPi.
[15:8] FWID = 0x0, for an FSG pulse that is one CLKG cycle wide. The
McBSPi.
[11:0] FPER field are not programmed; the period from the start of a
frame-synchronization pulse to the start of the next pulse is determined by the arrival of the next
inactive-to-active transition on the mcbspi_fsr pin.
3107
SWPU177N – December 2009 – Revised November 2010
Multi-Channel Buffered Serial Port
Copyright © 2009–2010, Texas Instruments Incorporated
