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General-Purpose Interface Register Manual
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Table 25-12. GPIO6 Register Summary (continued)
Register Name
Type
Register Width
Address Offset
Physical Address
(Bits)
RW
32
0x074
0x4905 8074
RW
32
0x080
0x4905 8080
RW
32
0x084
0x4905 8084
RW
32
0x090
0x4905 8090
RW
32
0x094
0x4905 8094
The write latency for all the R/W registers is immediate (with respect to the interface clock).
NOTE:
When two write accesses in the GPIOi.
register are performed in
less than two debounce clock cycles (32 kHz) plus four interface clock cycles, the first write
access latency is immediate, but the second write access is acknowledged only after this
interval ends.
In the register descriptions in this section, when one single register carries an individual configuration or
setting for all the channels of the module, 1 bit in the register is dedicated to each channel. The bit and the
corresponding channel are identified with the same number: Bit 0 refers to channel 0, bit 1 refers to
channel 1, and so on, up to 31.
25.6.2 Register Descriptions
through
describe the register bits.
Table 25-13. GPIO_REVISION
Address Offset
0x000
Physical Address
0x4831 0000
Instance
GPIO1
0x4905 0000
GPIO2
0x4905 2000
GPIO3
0x4905 4000
GPIO4
0x4905 6000
GPIO5
0x4905 8000
GPIO6
Description
This register contains the IP revision code.
Type
R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
GPIOREVISION
Bits
Field Name
Description
Type
Reset
31:8
RESERVED
Read returns 0
R
0x000000
7:0
GPIOREVISION
IP revision
R
See
(1)
[7:4] Major revision
[3:0] Minor revision
Examples: 0x10 for 1.0, 0x21 for 2.1
(1)
TI internal data
Table 25-14. Register Call Summary for Register GPIO_REVISION
General-Purpose Interface Register Manual
•
General-Purpose Interface Register Mapping Summary
3490General-Purpose Interface
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated