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General-Purpose Interface Register Manual
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Table 25-9. GPIO3 Register Summary (continued)
Register Name
Type
Register Width
Address Offset
Physical Address
(Bits)
RW
32
0x054
0x4905 2054
RW
32
0x060
0x4905 2060
RW
32
0x064
0x4905 2064
RW
32
0x070
0x4905 2070
RW
32
0x074
0x4905 2074
RW
32
0x080
0x4905 2080
RW
32
0x084
0x4905 2084
RW
32
0x090
0x4905 2090
RW
32
0x094
0x4905 2094
Table 25-10. GPIO4 Register Summary
Register Name
Type
Register Width
Address Offset
Physical Address
(Bits)
R
32
0x000
0x4905 4000
RW
32
0x010
0x4905 4010
R
32
0x014
0x4905 4014
RW
32
0x018
0x4905 4018
RW
32
0x01C
0x4905 401C
RW
32
0x020
0x4905 4020
RW
32
0x028
0x4905 4028
RW
32
0x02C
0x4905 402C
RW
32
0x030
0x4905 4030
RW
32
0x034
0x4905 4034
R
32
0x038
0x4905 4038
RW
32
0x03C
0x4905 403C
RW
32
0x040
0x4905 4040
RW
32
0x044
0x4905 4044
RW
32
0x048
0x4905 4048
RW
32
0x04C
0x4905 404C
RW
32
0x050
0x4905 4050
RW
32
0x054
0x4905 4054
RW
32
0x060
0x4905 4060
RW
32
0x064
0x4905 4064
RW
32
0x070
0x4905 4070
RW
32
0x074
0x4905 4074
RW
32
0x080
0x4905 4080
RW
32
0x084
0x4905 4084
RW
32
0x090
0x4905 4090
RW
32
0x094
0x4905 4094
Table 25-11. GPIO5 Register Summary
Register Name
Type
Register Width
Address Offset
Physical Address
(Bits)
R
32
0x000
0x4905 6000
RW
32
0x010
0x4905 6010
R
32
0x014
0x4905 6014
RW
32
0x018
0x4905 6018
3488
General-Purpose Interface
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated