CS0
CS1
SDRC.SDRC_SHARING[14:9]
CSnMUXCFGfield
Data lane and
endianism control
Endianism
control
Config mux and endianism
sdrc-012
Interconnect
data[63:48]
Interconnect
data[47:32]
Interconnect
data[31:16]
Interconnect
data[15:0]
SDRC data_out[15(31):0]
Data_lane[15(31):0]
Public Version
SDRAM Controller (SDRC) Subsystem
www.ti.com
10.2.4.4.5.2 Endianness-Aware Unpacking
Data transactions can be either big or little endian; the transaction endianness is determined by an
in-band interconnect qualifier. Muxing 64-bit data to 16-/32-bit data is performed according to this qualifier.
For a 64-bit interconnect little-endian write transaction on a 16-/32-bit memory, Data[15(31):0] is written at
the lowest memory address, and Data[63:48(32)] is written at the highest memory address.
For a 64-bit interconnect big-endian write transaction on a 16-/32-bit memory, Data[15(31):0] is written at
the highest memory address, and Data[63:48(32)] is written at the lowest memory address.
shows the data multiplexing scheme.
Figure 10-55. Data Multiplexing Scheme
10.2.4.4.6 Data Demultiplexing During Read Operations
10.2.4.4.6.1 External Bus Combinations
The SDRC pin allocation scenarios are shown in
. These scenarios are defined on a per-CS
basis for maximum flexibility. The pin allocation configurations allow implementation of combinations of
16-/32-bit external interfaces. The data demultiplexer receives 16-/32-bit data from the relevant SDRC
data lane, and then performs a data packing function. The packing function formats the data into 64-, 32-,
16-, or 8-bit format. The data demultiplexer also steers the data from the appropriate data lane. The data
partitioning and data steering are determined by the SDRC.
[11:9] CSOMUXCFG and
SDRC.
[14:12] CS1MUXCFG bit fields.
shows the data demultiplexing scheme.
2254
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
