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CS0
S
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D
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S
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Data lane and endianism
control
Endianism
sdrc
data_in[15(31):0]
Config mux and endianism
align[63:48]
OCP data[63:0]
align[47:32]
align[31:16]
align[15:0]
data_lane[15(31):0]
sdrc-013
Public Version
www.ti.com
SDRAM Controller (SDRC) Subsystem
Figure 10-56. Data Demultiplexing Scheme
10.2.4.4.6.2 Endianness-Aware Packing
Data transactions can be big or little endian; their endianness is determined by an in-band interconnect
qualifier. Demuxing 16-/32-bit memory data to 64-bit interconnect data is performed according to this
qualifier.
For a 64-bit interconnect little-endian read transaction on a 16-/32-bit memory, Data[15(31):0] is read from
the lowest memory address, and Data[63:48(32)] is read from the highest memory address.
For a 64-bit interconnect big-endian read transaction on a 16-/32-bit memory, Data[15(31):0] is read from
the highest memory address, and Data[63:48(32)] is read from the lowest memory address.
To preserve data integrity in all situations, that is, regardless of the effective scalar size of the transferred
data (byte, Word16, Word32, or DWord64), the endianness specified during the read operation must
match that specified during the write operation. If there is no match, the packing and unpacking operations
are not consistent. There is no attempt to perform endianness conversion in the SDRC; only endian-aware
width conversion is performed.
2255
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated