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IVA2.2 Subsystem Basic Programming Model
Setting these 3 bits to 1 performs a software reset to the IVA2.2 subsystem.
The reset status is logged in the PRCM.RM_RSTST_IVA2[8] IVA2_SW_RST1 read-only bit for
IVA2_RST1 software reset, the PRCM.RM_RSTST_IVA2[9] IVA2_SW_RST2 read-only bit for IVA2_RST2
software reset, and the PRCM.RM_RSTST_IVA2[10] IVA2_SW_RST3 read-only bit for IVA2_RST3
software reset.
For a complete description of these PRCM registers, see
, Power, Reset, and Clock
Management.
NOTE:
Software reset can be applied only while the IVA2.2 subsystem is in clock-off mode.
5.4.10.3 Power-Down and Wake-Up Management
•
DSP megamodule power-down controller (PDC)
The DSP megamodule embeds a PDC block that allows power-down management by software.
Individual DSP megamodule blocks such as DSP CPU, PMC, DMC, EMC, and UMC can be powered
off by the PDC.
•
This software control is ensured by the IVA_SYS.
register:
–
By setting the IVA_SYS.
[16] GEMPD bit to 1, the user enables power-down management
during idle mode.
–
By setting the IVA_SYS.
xMCLOG[1:0] and IVA_SYS.
xMCMEM[1:0] fields (x =
{P, D, U}), the user controls the XMC clock-gating and standby memory modes. For example, DMC
is controlled with the IVA_SYS.
[5:4] DMCLOG and IVA_SYS.
[7:6] xMCMEM
fields.
–
The programming sequence for transition to clock-off state is as follows:
Before executing the IDLE instruction, the user must perform the following sequence:
1. Write 1 to the IVA_SYS.
[16] GEMPD bit (standby state); by default, the
xMCLOG[1:0] and IVA_SYS.
xMCMEM[1:0] (x = {P, D, U}) field
values are all 0x1, so that module clock gating is enabled and standby mode of memories is
statically activated after the IDLE instruction executes.
2. Mask all interrupts not intended to wake up the IVA2.2 subsystem.
3. Program the PRCM so that IVA2.2 clocks are cut on IVA2.2 standby. For more information, see
, Power, Reset, and Clock Management.
4. Read back all the written registers to ensure write completion.
The user must also ensure that no other instruction is executed parallel to the IDLE instruction.
When a clock stop request is asserted, the PDC_INT event (EVT118, see
) is generated
to the DSP megamodule IC module to inform the DSP CPU to initiate a power-down sequence. For
more information about interrupt management, see
, Interrupt Management.
•
Programming sequence for transition to power-off state:
Before executing the IDLE instruction, the user must perform the sequence shown in
.
797
SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
