D
iv
id
e
r
[2
]
m
u
x
mux
m
u
x
D
iv
id
e
r
[4
]
5
4
M
H
z
P
R
M
_
1
9
2
M
_
A
L
W
O
N
_
C
L
K
5
4
M
H
z
C
O
R
E
_
C
L
K
9
6
M
H
z
C
M
D
P
L
L
4
D
P
L
L
3
P
R
M
C
L
K
O
U
T
2
_
P
O
L
C
L
K
OU
T
2
_
E
N
C
lo
c
k
g
e
n
e
ra
to
r
D
iv
id
e
r
[1, 2
]
G
a
ti
n
g
/s
ta
te
c
o
n
tr
o
l
D
iv
id
e
r
[1, 2, 4
, 8,
16]
D
iv
id
e
r
[1, 2]
C
tr
l
D
iv
id
e
r
[1, 2
]
D
iv
id
e
r
[1
,
2
]
D
iv
id
e
r
[1
, 2
]
sys_altclk
sys_clkout2
CM_SYS_CLK
DPLL3_M2_CLK
DPLL3_M2X2_CLK
DPLL4_M2_CLK
DPLL4_M3_CLK
DSS_TV_FCLK
12M_FCLK
48M_FCLK
96M_FCLK
COREX2_CLK
DPLL2_FCLK
DPLL1_FCLK
CORE_CLK
L3_ICLK
L4_ICLK
RM_ICLK
(to PRM)
prcm-038
CM_96M_FCLK
D
P
L
L
5
DPLL5_M2_CLK
120M_FCLK
m
u
x
CM_SYS_CLK
Public Version
www.ti.com
PRCM Functional Description
Figure 3-39. CM Clock Generator Functional Overview
299
SWPU177N – December 2009 – Revised November 2010
Power, Reset, and Clock Management
Copyright © 2009–2010, Texas Instruments Incorporated