Texas Instruments OMAP36 Series, Technical Reference Manual

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PRCM Register Manual
Bits Field Name Description Type Reset
31:4 RESERVED Write 0s for future compatibility. Read returns 0. R 0x0000000
3 COREDOMAINWKUP_RST CORE domain wake-up reset RW 0x0
Read 0x0: No power domain wake-up reset.
Write 0x0: Status bit unchanged
Read 0x1: DSS domain has been reset following a CORE
power domain wake-up from OFF to ON.
Write 0x1: Status bit is cleared to 0.
2 DOMAINWKUP_RST Power domain wake-up reset RW 0x0
Read 0x0: Status bit unchanged
Write 0x0: No power domain wake-up reset.
Read 0x1: DSS domain has been reset following a DSS
power domain wake-up.
Write 0x1: Status bit is cleared to 0.
1 GLOBALWARM_RST Global warm reset RW 0x0
Read 0x0: No global warm reset.
Write 0x0: Status bit unchanged
Read 0x1: DISPLAY domain has been reset upon a
global warm reset
Write 0x1: Status bit is cleared to 0.
0 GLOBALCOLD_RST Global cold reset RW 0x1
Read 0x0: No global cold reset.
Write 0x0: Status bit unchanged
Read 0x1: DISPLAY domain has been reset upon a
global cold reset
Write 0x1: Status bit is cleared to 0.
Table 3-392. Register Call Summary for Register RM_RSTST_DSS
PRCM Basic Programming Model
• RM_RSTST_ <domain_name> (Reset Status Register) : [0]
PRCM Register Manual
• DSS_PRM Register Summary : [1]
Table 3-393. PM_WKEN_DSS
Address Offset 0x0000 00A0
Physical Address 0x4830 6EA0 Instance DSS_PRM
Description This register allows enabling/disabling modules wake-up events.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
EN_DSS
Bits Field Name Description Type Reset
31:1 RESERVED Write 0s for future compatibility. Read returns 0. R 0x00000000
0 EN_DSS DSS Wake-up enable RW 0x1
0x0: DSS wake-up is disabled
0x1: DSS wake-up event is enabled
603 SWPU177N – December 2009 – Revised November 2010 Power, Reset, and Clock Management
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