Intel 500 - DATASHEET REV 003 Datasheet Download

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Intel® Celeron® Processor 500

Series

Datasheet

For Platforms Based on Mobile Intel® 965 Express Chipset Family

January 2008

Revision 003

Document Number: 317665-003

Summary of Contents for 500 - DATASHEET REV 003

Page 1: ...Intel Celeron Processor 500 Series Datasheet For Platforms Based on Mobile Intel 965 Express Chipset Family January 2008 Revision 003 Document Number 317665 003...

Page 2: ...lities arising from future changes to them The information here is subject to change without notice Do not finalize a design with this information The products described in this document may contain d...

Page 3: ...r PSI Signal 15 3 Electrical Specifications 17 3 1 Power and Ground Pins 17 3 2 FSB Clock BCLK 1 0 and Processor Clocking 17 3 3 Voltage Identification 17 3 4 Catastrophic Thermal Protection 21 3 5 Re...

Page 4: ...r Absolute Maximum Ratings 24 6 DC Voltage and Current Specifications 24 7 FSB Differential BCLK Specifications 26 8 AGTL Signal Group DC Specifications 27 9 CMOS Signal Group DC Specifications 28 10...

Page 5: ...vision History Document Number Revision Number Description Date 317666 001 Initial Release June 2007 317666 002 Corrected Figures 4 5 6 7 November 2007 317665 003 Added the Intel Celeron processor 560...

Page 6: ...6 Datasheet...

Page 7: ...itecture 533 MHz source synchronous front side bus FSB Supports Intel architecture with dynamic execution Data prefetch logic Micro FCPGA packaging technology MMX technology Streaming SIMD Extensions...

Page 8: ...logy on some Intel processors Front Side Bus FSB Refers to the interface between the processor and system core logic also known as the chipset components Intel 64 Technology 64 bit memory extensions t...

Page 9: ...obile Intel 965 Express Chipset Family Specification Update 316274 Intel I O Controller Hub 8 ICH8 Family Datasheet 313056 Intel I O Controller Hub 8 ICH8 Family Specification Update 313057 Intel 64 a...

Page 10: ...Introduction 10 Datasheet...

Page 11: ...gister block mapped in the processor s I O address space The P_LVLx I O reads are converted to equivalent MWAIT C state requests inside the processor and do not directly result in I O reads on the pro...

Page 12: ...on The system can generate a STPCLK while the processor is in the C1 AutoHALT Powerdown state When the system deasserts the STPCLK interrupt the processor returns execution to the HALT state The proce...

Page 13: ...tate in the C3 state The Monitor remains armed if it is configured All of the clocks in the processor core are stopped in the C3 state Because the core s caches are flushed the processor keeps the cor...

Page 14: ...e Sleep state is a low power state in which the processor maintains its context maintains the phase locked loop PLL and stops all internal clocks The Sleep state is entered through assertion of the SL...

Page 15: ...state the SLP pin must be deasserted to re enter the Stop Grant state While in Deep Sleep state the processor is incapable of responding to snoop transactions or latching interrupt signals No transit...

Page 16: ...Low Power Features 16 Datasheet...

Page 17: ...oltage determined by the VID Voltage ID pins 3 2 FSB Clock BCLK 1 0 and Processor Clocking BCLK 1 0 directly controls the FSB interface speed as well as the core frequency of the processor As in previ...

Page 18: ...0 1 3750 0 0 0 1 0 1 1 1 3625 0 0 0 1 1 0 0 1 3500 0 0 0 1 1 0 1 1 3375 0 0 0 1 1 1 0 1 3250 0 0 0 1 1 1 1 1 3125 0 0 1 0 0 0 0 1 3000 0 0 1 0 0 0 1 1 2875 0 0 1 0 0 1 0 1 2750 0 0 1 0 0 1 1 1 2625 0...

Page 19: ...0 0 8500 0 1 1 0 1 0 1 0 8375 0 1 1 0 1 1 0 0 8250 0 1 1 0 1 1 1 0 8125 0 1 1 1 0 0 0 0 8000 0 1 1 1 0 0 1 0 7875 0 1 1 1 0 1 0 0 7750 0 1 1 1 0 1 1 0 7625 0 1 1 1 1 0 0 0 7500 0 1 1 1 1 0 1 0 7375 0...

Page 20: ...0 0 3750 1 0 1 1 0 1 1 0 3625 1 0 1 1 1 0 0 0 3500 1 0 1 1 1 0 1 0 3375 1 0 1 1 1 1 0 0 3250 1 0 1 1 1 1 1 0 3125 1 1 0 0 0 0 0 0 3000 1 1 0 0 0 0 1 0 2875 1 1 0 0 0 1 0 0 2750 1 1 0 0 0 1 1 0 2625 1...

Page 21: ...s must remain unconnected Connection of these pins to VCC VSS or to any other signal including each other can result in component malfunction or incompatibility with future processors See Section 4 2...

Page 22: ...eters are specified because of a source synchronous data bus One set is for common clock signals that are dependent upon the rising edge of BCLK0 ADS HIT HITM etc and the second set is for the source...

Page 23: ...wever all of the CMOS signals are required to be asserted for at least three BCLKs in order for the processor to recognize them 3 9 Maximum Ratings Table 5 specifies absolute maximum and minimum ratin...

Page 24: ...ions for the CMOS group are listed in Table 9 Table 6 through Table 10 list the DC specifications and are valid only while meeting specifications for junction temperature clock frequency and input vol...

Page 25: ...and averaged over the duration of any change in current Specified by design characterization at nominal VCC Not 100 tested 7 Measured at the bulk capacitors on the motherboard 8 VCC BOOT tolerance sho...

Page 26: ...in note 2 Figure 3 Active VCC and ICC Loadline Standard Voltage ICC max VCC V VCC nom VCC nom 1 5 VR St Pt Error 1 VCC DC min VCC DC max VCC max VCC min 10 mV RIPPLE ICC A 0 Slope 2 1 mV A at package...

Page 27: ...eous VCCP 7 RTT is the on die termination resistance measured at VOL of the AGTL output driver Measured at 0 31 VCCP RTT is connected to VCCP on die Refer to processor I O buffer models for I V charac...

Page 28: ...p resistor to VCCP Please refer to platform design guide for details 4 For Vin between 0 V and VOH 5 CPAD includes die capacitance only No package parasitics are included Table 9 CMOS Signal Group DC...

Page 29: ...Mechanical Specifications and Pin Information 4 1 Package Mechanical Specifications The processor has two variants both available in a 478 pin Micro FCPGA package Package mechanical dimensions are sh...

Page 30: ...ecifications and Pin Information 30 Datasheet Figure 4 1 MB Fused Micro FCPGA Processor Package Drawing 1 of 2 Top View Front View Detail A Bottom View Side View P 0 1 1 0 2 1 1 1 1 1 1 3 4 5 6 1 1 0...

Page 31: ...Datasheet 31 Package Mechanical Specifications and Pin Information Figure 5 1 MB Fused Micro FCPGA Processor Package Drawing 2 of 2 Top View Bottom View Side View 0 406 0 305 0 25 C A M B 0 254 C M...

Page 32: ...Specifications and Pin Information 32 Datasheet Figure 6 1 MB Micro FCPGA Processor Package Drawing 1 of 2 Top View Front View Detail A Bottom View Side View oP 0 0 1 1 2 3 4 5 6 6 0 356 C A M B 0 25...

Page 33: ...Datasheet 33 Package Mechanical Specifications and Pin Information Figure 7 1 MB Micro FCPGA Processor Package Drawing 2 of 2 Top View Bottom View Side View 0 406 0 305 0 25 C A M B 0 254 C M...

Page 34: ...2 VSS BPRI HIT G H ADS REQ 1 VSS LOCK DEFER VSS H J A 9 VSS REQ 3 A 3 VSS VCCP J K VSS REQ 2 REQ 0 VSS A 6 VCCP K L REQ 4 A 13 VSS A 5 A 4 VSS L M ADSTB 0 VSS A 7 RSVD VSS VCCP M N VSS A 8 A 10 VSS R...

Page 35: ...BP 0 H J VCCP VSS D 11 D 10 VSS DSTBN 0 J K VCCP D 14 VSS D 8 D 17 VSS K L VSS D 22 D 20 VSS D 29 DSTBN 1 L M VCCP VSS D 23 D 21 VSS DSTBP 1 M N VCCP D 16 VSS DINV 1 D 31 VSS N P VSS D 26 D 25 VSS D 2...

Page 36: ...Package Mechanical Specifications and Pin Information 36 Datasheet This page is intentionally left blank...

Page 37: ...ource Synch Input Output A 25 T5 Source Synch Input Output A 26 T3 Source Synch Input Output A 27 W2 Source Synch Input Output A 28 W5 Source Synch Input Output A 29 Y4 Source Synch Input Output A 30...

Page 38: ...M23 Source Synch Input Output Table 13 Pin Listing by Pin Name Sheet 3 of 15 Pin Name Pin Number Signal Buffer Type Direction D 24 P25 Source Synch Input Output D 25 P23 Source Synch Input Output D 26...

Page 39: ...ommon Clock Input Output Table 13 Pin Listing by Pin Name Sheet 5 of 15 Pin Name Pin Number Signal Buffer Type Direction DSTBN 0 J26 Source Synch Input Output DSTBN 1 L26 Source Synch Input Output DST...

Page 40: ...A18 Power Other Table 13 Pin Listing by Pin Name Sheet 7 of 15 Pin Name Pin Number Signal Buffer Type Direction VCC A20 Power Other VCC AA7 Power Other VCC AA9 Power Other VCC AA10 Power Other VCC AA1...

Page 41: ...Other VCC E12 Power Other Table 13 Pin Listing by Pin Name Sheet 9 of 15 Pin Name Pin Number Signal Buffer Type Direction VCC E13 Power Other VCC E15 Power Other VCC E17 Power Other VCC E18 Power Oth...

Page 42: ...SS AD2 Power Other VSS AD5 Power Other Table 13 Pin Listing by Pin Name Sheet 11 of 15 Pin Name Pin Number Signal Buffer Type Direction VSS AD8 Power Other VSS AD11 Power Other VSS AD13 Power Other VS...

Page 43: ...VSS H24 Power Other VSS J2 Power Other Table 13 Pin Listing by Pin Name Sheet 13 of 15 Pin Name Pin Number Signal Buffer Type Direction VSS J5 Power Other VSS J22 Power Other VSS J25 Power Other VSS K...

Page 44: ...Input VSS A23 Power Other Table 13 Pin Listing by Pin Name Sheet 15 of 15 Pin Name Pin Number Signal Buffer Type Direction THRMDA A24 Power Other VSS A25 Power Other TEST6 A26 Test COMP 2 AA1 Power Ot...

Page 45: ...C7 Power Other VSS AC8 Power Other Table 14 Pin Listing by Pin Number Sheet 3 of 17 Pin Name Pin Number Signal Buffer Type Direction VCC AC9 Power Other VCC AC10 Power Other VSS AC11 Power Other VCC A...

Page 46: ...Power Other VCC AE20 Power Other Table 14 Pin Listing by Pin Number Sheet 5 of 17 Pin Name Pin Number Signal Buffer Type Direction D 58 AE21 Source Synch Input Output D 55 AE22 Source Synch Input Out...

Page 47: ...C C9 Power Other VCC C10 Power Other Table 14 Pin Listing by Pin Number Sheet 7 of 17 Pin Name Pin Number Signal Buffer Type Direction VSS C11 Power Other VCC C12 Power Other VCC C13 Power Other VSS C...

Page 48: ...ower Other D 6 E25 Source Synch Input Output Table 14 Pin Listing by Pin Number Sheet 9 of 17 Pin Name Pin Number Signal Buffer Type Direction D 2 E26 Source Synch Input Output BR0 F1 Common Clock Inp...

Page 49: ...put Output VSS J5 Power Other Table 14 Pin Listing by Pin Number Sheet 11 of 17 Pin Name Pin Number Signal Buffer Type Direction VCCP J6 Power Other VCCP J21 Power Other VSS J22 Power Other D 11 J23 S...

Page 50: ...1 N25 Source Synch Input Output VSS N26 Power Other Table 14 Pin Listing by Pin Number Sheet 13 of 17 Pin Name Pin Number Signal Buffer Type Direction A 15 P1 Source Synch Input Output A 12 P2 Source...

Page 51: ...31 V4 Source Synch Input Output Table 14 Pin Listing by Pin Number Sheet 15 of 17 Pin Name Pin Number Signal Buffer Type Direction VSS V5 Power Other VCCP V6 Power Other VCCP V21 Power Other VSS V22...

Page 52: ...et D 32 Y22 Source Synch Input Output D 42 Y23 Source Synch Input Output VSS Y24 Power Other D 40 Y25 Source Synch Input Output DSTBN 2 Y26 Source Synch Input Output Table 14 Pin Listing by Pin Number...

Page 53: ...pported in real mode A20M is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corre...

Page 54: ...ssociated with each combination The required frequency is determined by the processor chipset and clock synthesizer All agents must operate at the same frequency The Intel Celeron processor 500 series...

Page 55: ...polarity of the D 63 0 signals The DINV 3 0 signals are activated when the data on the data bus is inverted The bus agent inverts the data bus signals if more than half the bits within the covered gro...

Page 56: ...eak event For additional information on the pending break event functionality including identification of support of the feature and enable disable information refer to Volume 3 of the Intel 64 and IA...

Page 57: ...owever to ensure recognition of this signal following an Input Output Write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT must...

Page 58: ...to protect internal circuits against voltage sequencing issues It should be driven high throughout boundary scan operation For termination requirements please refer to the appropriate platform design...

Page 59: ...nsactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect...

Page 60: ...the silicon with little noise VID 6 0 Output VID 6 0 Voltage ID pins are used to support automatic selection of power supply voltages VCC Unlike some previous generations of processors these are CMOS...

Page 61: ...pecifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated 3 As measured by the activation of the on d...

Page 62: ...thermal diode by the thermal sensor is slower than the rate at which the TJ temperature can change Offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading may...

Page 63: ...re Kelvin 5 The series resistance RT is provided to allow for a more accurate measurement of the diode junction temperature RT as defined includes the pins of the processor but does not include any so...

Page 64: ...ct the designers usually select an ntrim value that more closely matches the behavior of the diodes in the processor If the processor diode ideality deviates from that of the ntrim each calculated tem...

Page 65: ...es Processor performance is decreased by the same amount as the duty cycle when the TCC is active The TCC may also be activated via on demand mode If bit 4 of the ACPI Intel Thermal Monitor control re...

Page 66: ...conditions are detectable via an Out Of Spec status bit This bit is also part of the DTS MSR When this bit is set the processor is operating out of specification and immediate shutdown of the system...

Page 67: ...for the PROCHOT signal is the thermal protection of voltage regulators VR System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR...

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