Public Version
L3 Interconnect
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Table 9-76. Protection Mechanism Common Register Summary
Register Name
Type
Register
PM_OCM_RAM
PM_OCM_ROM
Width
Physical
Physical
(Bits)
Address
Address
RW
64
0x6801 2820
0x6801 2C20
RW
64
0x6801 2828
0x6801 2C28
R
64
0x6801 2830
0x6801 2C30
R
64
0x6801 2838
0x6801 2C38
(1)
RW
64
0x6801 2848 + (0x20*i) 0x6801 2C48 + (0x20*i)
(1)
RW
64
0x6801 2850 + (0x20*i) 0x6801 2C50 + (0x20*i)
(1)
RW
64
0x6801 2858 + (0x20*i) 0x6801 2C58 + (0x20*i)
(2)
RW
64
0x6801 2860 +
0x6801 2C60 +
(0x20*k)
(0x20*k)
(1)
i = 0 to 1 for PM_OCM_ROM
i = 0 to 7 for PM_OCM_RAM
(2)
k = 1 to 1 for PM_OCM_ROM
k = 1 to 7 for PM_OCM_RAM
Table 9-77. Protection Mechanism Common Register Summary
Register Name
Type
Register
PM_MAD2D
PM_IVA2.2
Width
Physical
Physical
(Bits)
Address
Address
RW
64
0x6801 3020
0x6801 4020
RW
64
0x6801 3028
0x6801 4028
R
64
0x6801 3030
0x6801 4030
R
64
0x6801 3038
0x6801 4038
(1)
RW
64
0x6801 3048 + (0x20*i)
0x6801 4048 + (0x20*i)
(1)
RW
64
0x6801 3050 + (0x20*i)
0x6801 4050 + (0x20*i)
(1)
RW
64
0x6801 3058 + (0x20*i)
0x6801 4058 + (0x20*i)
(2)
RW
64
0x6801 3060 + (0x20*k)
0x6801 4060 + (0x20*k)
(1)
i = 0 to 7 for PM_MAD2D
i = 0 to 3 for PM_IVA2.2
(2)
k = 1 to 7 for PM_MAD2D
k = 1 to 3 for PM_IVA2.2
9.2.5.4.1 Protection Mechanism (PM) Registers Description
Table 9-78. L3_PM_ERROR_LOG
Address Offset
0x20
Physical Address
See
to
Description
This register logs errors detected by the protection mechanism.
Type
RW
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CODE
Reserved
REQ_INFO
INITID
REGION
CMD
MULTI
Reserved
Reserved
Reserved
SECONDARY
2044
Interconnect
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated