Texas Instruments OMAP36 Series, Technical Reference Manual

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L3 Interconnect
Table 9-91. L3_PM_WRITE_PERMISSION_i
Address Offset 0x058 + (0x20+i) Index i = 0 to 1 for PM_RT
i = 0 to 7 for PM_GPMC
i = 0 to 1 for PM_OCM_ROM
i = 0 to 3 for PM_IVA2
i = 0 to 7 for PM_OCM_RAM
Physical Address See Table 9-75 to Table 9-77
Description It configures protection region permissions for write incoming commands.
Type RW
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
DAP SGX
CAM MPU
SDMA
DISPSS
SAD2D
Reserved Reserved Reserved
IVA2_DMA
IVA2_MMU
USB_HS_Host
USB_HS_OTG
Bits Field Name Description Type Reset
63:15 Reserved Reserved R 0x0
14 SGX Write permission for the SGX RW See Table 9-93
13 Reserved Reserved RW 0x0
12 DAP Write permission for the DAP RW See Table 9-93
11 CAM Write permission for the CAMERA SS RW See Table 9-93
10 IVA2_MMU Write permission for the IVA2 MMU RW See Table 9-93
9 USB_HS_Host Write permission for the USB_HS_Host RW See Table 9-93
8 DISPSS Write permission for the DISPLAY SS RW See Table 9-93
7:6 Reserved Reserved RW 0x0
5 SAD2D Write permission for the SAD2D RW See Table 9-93
4 USB_HS_OTG Write permission for the USB_HS_OTG RW See Table 9-93
3 SDMA Write permission for the system DMA RW See Table 9-93
2 IVA2_DMA Write permission for the IVA2 RW See Table 9-93
1 MPU Write permission for the MPU RW See Table 9-93
0 Reserved Reserved RW 0x0
Table 9-92. Register Call Summary for Register L3_PM_WRITE_PERMISSION_i
L3 Interconnect
• Read and Write Permission : [0] [1]
• L3 Firewall Registers Overview : [2] [3]
• Typical Example of Firewall Programming Example : [4] [5] [6] [7] [8] [9] [10]
• Protection Mechanism (PM) : [11] [12] [13]
• Protection Mechanism (PM) Registers Description : [14]
Table 9-93 shows bit available in L3_PM_READ_PERMISSION_i and L3_PM_WRITE_PERMISSION_i
registers. All N/A are considered as reserved bits with a Read access.
2049 SWPU177N – December 2009 – Revised November 2010 Interconnect
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