Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 2011 / 3738

U
U
U
U
10
11
12
13
14
15
Unused
Unused
0x0C05
0x5 0x0
intc-021
Accessallowed?
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L3 Interconnect
Figure 9-6. Example of REQ_INFO_PERMISSION Register
As another example, to configure a target accessible only for data and in a user mode, Reqbit 0, 1, 2 and
3 must be set. Therefore, the
L3_PM_REQ_INFO_PERMISSION_i register must be set to 0x000F.
9.2.3.3.5 L3 Firewall Registers Overview
Table 9-23 lists the L3 firewall permission-setting registers. L3_PM_ADDR_MATCH_k , which is shown in
this table, is not an accessible register.
Table 9-23. L3 Firewall Permission-Setting Registers
Register Name Register Field Parameter Comments Region
Field Modifiability Comments
Name
Region 0 This region is the
default region.
L3_PM_ADDR_MATCH_k ADDR_SPACE[2:0] Hard coded Corresponds to all the target
The default setting
(k=0) memory space
can be changed
SIZE[7:3] Hard coded Corresponds to all the target only with correct
memory space
access according
to L3 RT register.
Reserved Default region: Level 0
BASE_ADDR[63:10] Hard coded Target-dependent
L3_PM_REQ_INFO_PERMISS REQ_INFO[15 :0] Yes Type of access permitted.
ION_i See Table 9-22 .
(i=0)
L3_PM_READ_PERMISSION_ READ_PERMISSION[15: Yes Initiator read permission,
i 0] depending on connections.
(i=0) See Table 9-14 .
L3_PM_WRITE_PERMISSION WRITE_PERMISSION[15 Yes Initiator write permission,
_i :0] depending on connections.
(i=0) See Table 9-14 .
2011 SWPU177N – December 2009 – Revised November 2010 Interconnect
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