Texas Instruments OMAP36 Series, Technical Reference Manual

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L3 Interconnect
Example 1
In this example, the MPU interrupt handler detects an error from the L3 interconnect. A read access from
the
L3_SI_FLAG_STATUS_0 register reports a value of 0x40000. As described in Table 9-29 , the error
detected is a burst time-out from the sDMA read port.
As with any time-out error, the affected module is now considered to be out-of-service. If necessary, the
error can be cleared by sending a soft reset command to the agent (set CORE_RESET bit
L3_IA_AGENT_CONTROL [0] to 1, and then to 0). During this time the initiator is off-line. Although the rest
of the system still behaves normally, a time-out error is usually severe enough to require a complete reset
of the chip.
Before resetting the agent or the system, the error log registers can learn the status of the interconnect
and determine the type of failure. Reading the IA_SDMA_RD.
L3_IA_AGENT_STATUS register shows
whether the time-out was detected during a burst or during a read/write sequence.
Example 2
In this example, the MPU interrupt controller detects an error from the L3 interconnect. A read access from
the
L3_SI_FLAG_STATUS_0 register reports a value of 0x100. This is a functional error from the IVA2.2
subsystem initiator.
The IA_IVA2.2. L3_IA_ERROR_LOG register should be read next. The value stored in it is
0x12_0400_1302.
• CMD field IA_IVA2.2. L3_IA_ERROR_LOG [2:0]: Value 0x2. Not applicable for an in-band error.
• INITID field IA_IVA2.2. L3_IA_ERROR_LOG [15:8]: Value 0x13. The origin of the error is the IVA2.2
subsystem sDMA.
• CODE field IA_IVA2.2. L3_IA_ERROR_LOG [27:24]: Value 0x4. Error is an in-band error.
• SECONDARY bit IA_IVA2.2. L3_IA_ERROR_LOG [30]: Value 0x0. The error is functional.
• MULTI bit IA_IVA2.2. L3_IA_ERROR_LOG [31]: Value 0x0. No additional error has been detected.
• REQ_INFO field IA_IVA2.2. L3_IA_ERROR_LOG [43:32]: Value 0x12. Not applicable for an in-band
error.
There is no simple way to determine which target originated the in-band error. An SError assertion or a
request time-out would have been detected and logged in the
L3_SI_FLAG_STATUS_0 register. Because
no such error is asserted (bits 60:48 are still 0), the error can only be a firewall error or have originated in
the target itself. The user must read all of the PM_xxx.
L3_PM_ERROR_LOG registers.
CAUTION
The PM register blocks are sensitive registers and are usually protected.
Ensure that the processor used to debug the error is allowed to access these
registers. If not, the access will be rejected and another error will be generated.
All PM_xxx. L3_PM_ERROR_LOG registers are clear (bits 27:24 equal 0x0) except for
PM_OCMRAM. L3_PM_ERROR_LOG , which reads 0x0302_1301. The error occurred while trying to
access the OCM RAM.
NOTE: If all PM_xxx. L3_PM_ERROR_LOG registers are clear, the error is unrelated to the
interconnect. Further analysis must be done in the targets.
• Bits 27:24: Value 0x3. There is a protection error.
• Bits 2:0: Value 0x1. The command was a posted write.
• Bits 6:4: Value 0x0. The address is protected by Region 0 (default region) of the firewall.
• Bits 15:8: Value 0x13. The origin of the error is the IVA2.2, thread 2. This is consistent with the error
log on the initiator side, and confirms this error report is the correct one.
• Bits 20:16: Value 0x2. The protection parameters were data, debug, and user.
• Bit 31: Value 0x0. This is the only error detected.
2023 SWPU177N – December 2009 – Revised November 2010 Interconnect
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