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L3 Interconnect
Table 9-98. L3_SI_CONTROL
Address Offset
0x020
Physical Address
0x6800 0420
Instance
SI
Description
Control of register and sideband interconnect
Type
RW
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Reserved
Reserved
CLOCK_GATE_DISABLE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
Bits
Field Name
Description
Type
Reset
63:57
Reserved
Reserved for future use
R
0x00
56
CLOCK_GATE_DISAB
Overrides fine grained hardware clock gating in register and
RW
0
LE
sideband interconnect
0x0: Normal clock gating
0x1: Clock gating disabled
55:0
Reserved
Reserved for future use
R
0x00000000000000
Table 9-99. Register Call Summary for Register L3_SI_CONTROL
L3 Interconnect
•
Table 9-100. L3_SI_FLAG_STATUS_0
Address Offset
0x110
Physical Address
0x6800 0510
Instance
SI
Description
They are used to observe the individual bits that make up a composite interconnect flag.
Type
R
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
STATUS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
STATUS
Bits
Field Name
Description
Type
Reset
63:0
STATUS
Status of sideband signals making up composite interconnect flag
R
0x0000000000000000
for application. See
2053
SWPU177N – December 2009 – Revised November 2010
Interconnect
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